The present invention relates to a film for semiconductor device production, which includes: a separator; and a plurality of adhesive layer-attached dicing tapes each including a dicing tape and an adhesive layer laminated on the dicing tape, which are laminated on the separator at a predetermined interval in such a manner that the adhesive layer attaches to the separator, in which the separator has a cut formed along the outer periphery of the dicing tape, and the depth of the cut is at most ⅔ of the thickness of the separator.

An energy storage device for an integrated circuit carrier package. One or more energy storage elements have contact elements arranged thereon that include an anode, a cathode, and an isolated common pad. The energy storage element is configured for arrangement in a stack of energy storage elements in which the isolated common pad is shorted to one of the anode or the cathode by bonded conductive interconnects.

A support including a heat resistant film layer and a resin layer, wherein the heat resistant film layer is laminated on at least one side (a first side) of the resin layer, and the resin layer is in a semi-cured state (B stage).

An energy storage device for an integrated circuit carrier package. One or more energy storage elements have contact elements arranged thereon that include an anode, a cathode, and an isolated common pad. The energy storage element is configured for arrangement in a stack of energy storage elements in which the isolated common pad is shorted to one of the anode or the cathode by bonded conductive interconnects.

The present disclosure provides methods to integrate piezoelectric micromachined ultrasonic transducer (pMUT) arrays with an application-specific integrated circuit (ASIC) using thermocompression or eutectic/solder bonding. In an aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using thermocompression, wherein any set of individual PMUTs of PMUT array is addressable. In another aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using eutectic or solder bonding, wherein any set of individual PMUTs of the PMUT array is addressable.

The present disclosure provides methods to integrate piezoelectric micromachined ultrasonic transducer (pMUT) arrays with an application-specific integrated circuit (ASIC) using thermocompression or eutectic/solder bonding. In an aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using thermocompression, wherein any set of individual PMUTs of PMUT array is addressable. In another aspect, the present disclosure provides a device comprising a first substrate and a second substrate, the first substrate comprising a pMUT array and the second substrate comprising an electrical circuit, wherein the first substrate and the second substrate are bonded together using eutectic or solder bonding, wherein any set of individual PMUTs of the PMUT array is addressable.

A method of manufacturing a multi-layer wafer is provided. At least one stress compensating polymer layer is applied to at least one of two heterogeneous wafers. The stress compensating polymer layer is low temperature bonded to the other of the two heterogeneous wafers to form a multi-layer wafer pair. Channels are created between die on at least one of the two heterogeneous wafers. The channels are back filled with one of oxide or polymer to create a channel oxide deposition.

A support including a heat resistant film layer and a resin layer, wherein the heat resistant film layer is laminated on at least one side (a first side) of the resin layer, and the resin layer is in a semi-cured state (B stage).

A solder reflow apparatus includes a vapor generating chamber configured to accommodate a heat transfer fluid and to accommodate saturated vapor generated by heating the heat transfer fluid; a heater configured to heat the heat transfer fluid accommodated in the vapor generating chamber; a substrate stage configured to be movable upward and downward within the vapor generating chamber, the substrate stage including a seating surface; vapor passages penetrating the substrate stage and configured to allow the vapor to move therethrough; and suction passages penetrating the substrate stage to be open to the seating surface and in which at least a partial vacuum is generated.

A multi-layer wafer and method of manufacturing such wafer are provided. The method includes applying at least one stress compensating polymer layer to at least one of two heterogeneous wafers and low temperature bonding the two heterogeneous wafers to bond the stress compensating polymer layer to the other of the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, at least one of the heterogeneous wafers having a stress compensating polymer layer. The two heterogeneous wafers are low temperature bonded together to bond the stress compensating polymer layer to the other of the two heterogeneous wafers.