Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chip structures with electrical overstress protection are disclosed. LED chip structures are disclosed that include built-in electrical overstress protection. An exemplary LED chip may include an active LED structure that is arranged as a primary light-emitting structure and a separate active LED structure that is arranged as an electrical overstress protection structure. The electrical overstress protection structure may be electrically connected in reverse relative to the primary light-emitting structure. In this manner, under normal operating conditions, forward current will flow through the primary light-emitting structure to generate desired light emissions, and during an electrical overstress event, reverse current may flow through the electrical overstress protection structure, thereby protecting the light-emitting structure from damage.

Solid-state lighting devices including light-emitting diodes (LEDs) and more particularly LED chip structures with electrical overstress protection are disclosed. LED chip structures are disclosed that include built-in electrical overstress protection. An exemplary LED chip may include an active LED structure that is arranged as a primary light-emitting structure and a separate active LED structure that is arranged as an electrical overstress protection structure. The electrical overstress protection structure may be electrically connected in reverse relative to the primary light-emitting structure. In this manner, under normal operating conditions, forward current will flow through the primary light-emitting structure to generate desired light emissions, and during an electrical overstress event, reverse current may flow through the electrical overstress protection structure, thereby protecting the light-emitting structure from damage.

A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.

A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.

A semiconductor device assembly includes a substrate and a die coupled to the substrate, the die including a first contact pad electrically coupled to a first circuit on the die including an active circuit element, a first TSV electrically coupling the first contact pad to a first backside contact pad, and a second contact pad electrically coupled to a second circuit including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first and second contact pads. The assembly can further include a second die including a third contact pad electrically coupled to a third circuit including a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad, but electrically disconnected from the fourth contact pad.

A chip package including a substrate having an upper surface, a lower surface, and a sidewall surface that is at the edge of the substrate is provided. The substrate includes a sensor device therein and adjacent to the upper surface thereof. The chip package further includes light-shielding layer disposed over the sidewall surface of the substrate and extends along the edge of the substrate to surround the sensor device. The chip package further includes a cover plate disposed over the upper surface of the substrate and a spacer layer disposed between the substrate and the cover plate. A method of forming the chip package is also provided.

A chip package including a substrate having an upper surface, a lower surface, and a sidewall surface that is at the edge of the substrate is provided. The substrate includes a sensor device therein and adjacent to the upper surface thereof. The chip package further includes light-shielding layer disposed over the sidewall surface of the substrate and extends along the edge of the substrate to surround the sensor device. The chip package further includes a cover plate disposed over the upper surface of the substrate and a spacer layer disposed between the substrate and the cover plate. A method of forming the chip package is also provided.