Electronic assembly methods and structures are described. In an embodiment, an electronic assembly method includes bringing together an electronic component and a routing substrate, and directing a large area photonic soldering light pulse toward the electronic component to bond the electronic component to the routing substrate.

Electronic assembly methods and structures are described. In an embodiment, an electronic assembly method includes bringing together an electronic component and a routing substrate, and directing a large area photonic soldering light pulse toward the electronic component to bond the electronic component to the routing substrate.

Electronic assembly methods and structures are described. In an embodiment, an electronic assembly method includes bringing together an electronic component and a routing substrate, and directing a large area photonic soldering light pulse toward the electronic component to bond the electronic component to the routing substrate.

An apparatus and method for soldering chips to a substrate. A substrate and two or more different chips having different heating properties are provided. A solder material is disposed between the chips and the substrate. A flash lamp generates a light pulse for heating the chips, wherein the solder material is at least partially melted by contact with the heated chips. A masking device is disposed between the flash lamp and the chips causing different light intensities in different areas of the light pulse passing the masking device thereby heating the chips with different light intensities. This may compensate the different heating properties to reduce a spread in temperature between the chips as a result of the heating by the light pulse.

Electronic assembly methods and structures are described. In an embodiment, an electronic assembly method includes bringing together an electronic component and a routing substrate, and directing a large area photonic soldering light pulse toward the electronic component to bond the electronic component to the routing substrate.

A substrate (3) and two or more different chips (1a, 1b) having different heating properties (e.g. caused by different dimensions (surface area and/or thickness), heat capacity (C1, C2), absorptivity, conductivity, number and/or size of solder bonds) are provided. A solder material (2) is disposed between the chips (1a, 1b) and the substrate (3). A flash lamp (5) generates a light pulse (6) for heating the chips (1a, 1b), wherein the solder material (2) is at least partially melted by contact with the heated chips (1a, 1b). A masking device (7) is disposed between the flash lamp (5) and the chips (1a, 1b) causing different light intensities (1a, 1b) in different areas (6a, 6b) of the light pulse (6) passing the masking device (7), thereby heating the chips (1a, 1b) with different light intensities (1a, 1b). This may compensate the different heating properties to reduce a spread in temperature between the chips (1a, 1b) as a result of the heating by the light pulse (6). The chips (1a, 1b) may be releasably carried by a chip carrier disposed between the flash lamp (5) and the substrate (3) before being positioned on the substrate (3), wherein the light (6a, 6b) of the light pulse (6) transmitted by the masking device (7) is projected onto the chips (1a, 1b) held by the chip carrier for heating the chips (1a, 1b), releasing them from the chip carrier and transferring them to the substrate (3), wherein the heated chips (1a, 1b) cause melting of the solder material (2) between the chips (1a, 1b) and the substrate (3) for attaching the chips (1a, 1b) to the substrate (3).

A method includes forming a die, which further includes forming a first through-via and a second through-via extending from a front side of a semiconductor substrate into the semiconductor substrate. The first through-via and the second through-via are connected to a first integrated circuit device and a second integrated circuit device, respectively, in the die. A backside grinding process is performed to reveal the first through-via and the second through-via. A backside redistribution line is formed to physically join to both of the first through-via and the second through-via.