A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked vias in the plurality of dielectric layers with the stacked vias forming a continuous electrical connection penetrating through the plurality of dielectric layers, forming a dielectric layer over the stacked vias and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding.

A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked vias in the plurality of dielectric layers with the stacked vias forming a continuous electrical connection penetrating through the plurality of dielectric layers, forming a dielectric layer over the stacked vias and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding.

An electronic device is provided in the present disclosure. The electronic device includes a substrate and a light emitting diode. The light emitting diode is bonded to the substrate through a solder alloy. The solder alloy includes tin and a metal element M, and the metal element M is one of the indium and bismuth. The atomic percentage of tin in the sum of tin and the metal element M ranges from 60% to 90% in the solder alloy.

An electronic device is provided in the present disclosure. The electronic device includes a substrate and a light emitting diode. The light emitting diode is bonded to the substrate through a solder alloy. The solder alloy includes tin and a metal element M, and the metal element M is one of the indium and bismuth. The atomic percentage of tin in the sum of tin and the metal element M ranges from 60% to 90% in the solder alloy.

A light-emitting device includes: a light-emitting element including a first surface provided as a light extraction surface, a second surface opposite to the first surface, a plurality of third surfaces between the first surface and the second surface, and a positive electrode and a negative electrode at the second surface; a light-transmissive member disposed at the first surface; and a bonding member disposed between the light-emitting element and the light-transmissive member and covering from the first surface to the plurality of third surfaces of the light-emitting element to bond the light-emitting element and the light-transmissive member. The bonding member is made of a resin that contains nanoparticles. The nanoparticles have a particle diameter of 1 nm or more and 30 nm or less and a content of 10 mass % or more and 20 mass % or less.

A light-emitting device includes: a light-emitting element including a first surface provided as a light extraction surface, a second surface opposite to the first surface, a plurality of third surfaces between the first surface and the second surface, and a positive electrode and a negative electrode at the second surface; a light-transmissive member disposed at the first surface; and a bonding member disposed between the light-emitting element and the light-transmissive member and covering from the first surface to the plurality of third surfaces of the light-emitting element to bond the light-emitting element and the light-transmissive member. The bonding member is made of a resin that contains nanoparticles. The nanoparticles have a particle diameter of 1 nm or more and 30 nm or less and a content of 10 mass % or more and 20 mass % or less.

A package structure is provided. The package structure includes an interposer substrate including an insulating structure, a conductive pad, a first conducive line, and a first conductive via structure. The package structure includes an electronic device bonded to the conductive pad. The package structure includes a chip structure bonded to the first end portion of the first conductive via structure. The package structure includes a first conductive bump connected between the chip structure and the first end portion of the first conductive via structure. The first end portion protrudes into the first conductive bump and is in direct contact with the first conductive bump.

A package structure is provided. The package structure includes an interposer substrate including an insulating structure, a conductive pad, a first conducive line, and a first conductive via structure. The package structure includes an electronic device bonded to the conductive pad. The package structure includes a chip structure bonded to the first end portion of the first conductive via structure. The package structure includes a first conductive bump connected between the chip structure and the first end portion of the first conductive via structure. The first end portion protrudes into the first conductive bump and is in direct contact with the first conductive bump.

A semiconductor package structure is provided. The semiconductor package structure includes a carrier substrate, an interposer substrate, a semiconductor device, a lid, and a thermal interface material. The interposer substrate is disposed on the carrier substrate. The semiconductor device is disposed on the interposer substrate. The lid is disposed on the carrier substrate to cover the semiconductor device. The thermal interface material is disposed between the lid and the semiconductor device. A first recess is formed on a lower surface of the lid facing the semiconductor device, and the first recess overlaps the semiconductor device in a top view.

A semiconductor package structure is provided. The semiconductor package structure includes a carrier substrate, an interposer substrate, a semiconductor device, a lid, and a thermal interface material. The interposer substrate is disposed on the carrier substrate. The semiconductor device is disposed on the interposer substrate. The lid is disposed on the carrier substrate to cover the semiconductor device. The thermal interface material is disposed between the lid and the semiconductor device. A first recess is formed on a lower surface of the lid facing the semiconductor device, and the first recess overlaps the semiconductor device in a top view.