In some implementations, a vertical cavity surface emitting laser (VCSEL) package may include a substrate. The VCSEL package may include a VCSEL disposed on a surface of the substrate. The VCSEL package may include a VCSEL driver disposed on the surface of the substrate. The VCSEL package may include an embedded capacitor electrically connected to the VCSEL and the VCSEL driver. The embedded capacitor may be formed from a subset of layers of the substrate. The capacitor may be associated with a first capacitance that is different from a second capacitance of at least one other capacitor associated with the substrate.

In some implementations, a vertical cavity surface emitting laser (VCSEL) package may include a substrate. The VCSEL package may include a VCSEL disposed on a surface of the substrate. The VCSEL package may include a VCSEL driver disposed on the surface of the substrate. The VCSEL package may include an embedded capacitor electrically connected to the VCSEL and the VCSEL driver. The embedded capacitor may be formed from a subset of layers of the substrate. The capacitor may be associated with a first capacitance that is different from a second capacitance of at least one other capacitor associated with the substrate.

A display device includes first pixel circuit unit, second pixel circuit unit, third pixel circuit unit, and fourth pixel circuit unit spaced from one another, first pixel electrode on the first pixel circuit unit, second pixel electrode on the second pixel circuit unit, third pixel electrode on the third pixel circuit unit, fourth pixel electrode on the fourth pixel circuit unit, first light-emitting element electrically connected to the first pixel electrode, the first light-emitting element configured to emit first light, second light-emitting element electrically connected to the second pixel electrode, the second light-emitting element configured to emit second light, and third light-emitting element electrically connected to the third pixel electrode, the third light-emitting element configured to emit third light. A length of the first light-emitting element in a first direction is greater than each of a length of the second and third light-emitting elements in the first direction.

In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.

A semiconductor device includes an interlayer insulating layer disposed on a substrate; a plurality of middle interconnections disposed in the interlayer insulating layer; a pad disposed on the interlayer insulating layer; an upper interconnection disposed on the interlayer insulating layer; a protective insulating layer covering an edge of the pad, the upper interconnection, and a horizontal gap between the pad and the upper interconnection, the protective insulating layer having an opening on the pad; and a bump disposed on the pad, the bump extending on the protective insulating layer and overlapping the upper interconnection from a top-down view. At least one of the plurality of middle interconnections from among middle interconnections vertically closest to the pad has a first vertical thickness, the pad has a second vertical thickness that is twice to 100 times the first vertical thickness, a length of the gap between the pad and the upper interconnection is 1 μm or more, and an upper surface of the protective insulating layer is planar.

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

A semiconductor package includes a semiconductor die including circuitry electrically coupled to bond pads that is mounted onto a leadframe. The leadframe includes a plurality of leads and a dam bar having a transverse portion that extends between adjoining ones of the leads. The bond pads are electrically connected to the plurality of leads. A raised dam pattern is on the dam bar or on an edge of an exposed portion of a top side clip of the semiconductor package that is positioned above and connects to the semiconductor die. The raised dam pattern includes a first material that is different relative to the material of the dam bar or the clip. A mold material encapsulates the semiconductor die.

A semiconductor package includes a semiconductor die including circuitry electrically coupled to bond pads that is mounted onto a leadframe. The leadframe includes a plurality of leads and a dam bar having a transverse portion that extends between adjoining ones of the leads. The bond pads are electrically connected to the plurality of leads. A raised dam pattern is on the dam bar or on an edge of an exposed portion of a top side clip of the semiconductor package that is positioned above and connects to the semiconductor die. The raised dam pattern includes a first material that is different relative to the material of the dam bar or the clip. A mold material encapsulates the semiconductor die.

In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.