A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a metal sintered material such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.

A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern arranged on an upper surface of the insulating plate and a heat dissipating plate arranged on a lower surface of the insulating plate. The semiconductor module also includes a semiconductor device having a collector electrode arranged on its upper surface, having an emitter electrode and a gate electrode arranged on its lower surface, and bumps respectively bonding the emitter electrode and the gate electrode to an upper surface of the circuit pattern. Each of the bumps is made of a metal sintered material such that the bump is formed to be constricted in its middle portion in a thickness direction orthogonal to a surface of the insulating plate.

Various embodiments of the teachings herein include a method for joining and insulating a power electronic semiconductor component with contact surfaces to a substrate. In some embodiments, the method includes: preparing the substrate with a metallization defining an installation slot having joining material, wherein the substrate comprises an organic or a ceramic wiring support; arranging an electrically insulating film and the semiconductor component on the substrate, such that the contact surfaces of the semiconductor component facing the substrate are omitted from the film and regions of the semiconductor component exposed by the contact surfaces are insulated at least in part by the film from the substrate and from the contact surfaces; and joining the semiconductor component to the substrate and electrically insulating the semiconductor component at least in part by the film in one step.

When a semiconductor element and a wiring board are connected to each other, connection at a minute pitch is performed while securing reliability.

In a semiconductor device, a semiconductor element and a wiring board are connected to each other. A bump is formed on an electrode in either the semiconductor element or the wiring board. This bump contains metal nanoparticles as a component. The bump may be formed by sintering the metal nanoparticles that are applied. Furthermore, the metal nanoparticles may be applied and sintered a plurality of times to form a plurality of layers. A connection between the semiconductor element and the wiring board may be formed by sintering the other metal nanoparticles that are applied.

A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern on an upper surface of the insulating plate and a heat dissipating plate on a lower surface of the insulating plate. The module further includes a semiconductor device having upper and lower surfaces, and including a collector electrode on the device upper surface, an emitter electrode and a gate electrode on the device lower surface, and the emitter electrode and the gate electrode each being bonded to an upper surface of the circuit pattern via a bump, and a block electrode bonded to the collector electrode. The block electrode includes a flat plate portion covering over the semiconductor device, and a pair of projecting portions projecting toward the circuit pattern from both ends of the flat plate portion in a thickness direction orthogonal to a surface of the insulating plate, and being bonded to the circuit pattern.

A semiconductor module includes a laminated substrate having an insulating plate, a circuit pattern on an upper surface of the insulating plate and a heat dissipating plate on a lower surface of the insulating plate. The module further includes a semiconductor device having upper and lower surfaces, and including a collector electrode on the device upper surface, an emitter electrode and a gate electrode on the device lower surface, and the emitter electrode and the gate electrode each being bonded to an upper surface of the circuit pattern via a bump, and a block electrode bonded to the collector electrode. The block electrode includes a flat plate portion covering over the semiconductor device, and a pair of projecting portions projecting toward the circuit pattern from both ends of the flat plate portion in a thickness direction orthogonal to a surface of the insulating plate, and being bonded to the circuit pattern.

This application relates to semiconductor manufacturing, and more particularly to an interconnect structure for semiconductors with an ultra-fine pitch and a forming method thereof. The forming method includes: preparing copper nanoparticles using a vapor deposition device, where coupling parameters of the vapor deposition device are adjusted to control an initial particle size of the copper nanoparticles; depositing the copper nanoparticles on a substrate; invertedly placing a chip with copper pillars as I/O ports on the substrate; and subjecting the chip and the substrate to hot-pressing sintering to enable the bonding.

Provided is a method for producing a joined body, the method including a first step of preparing a laminated body which includes a first member having a metal pillar provided on a surface thereof, a second member having an electrode pad provided on a surface thereof, and a joining material provided between the metal pillar and the electrode pad and containing metal particles and an organic compound, and a second step of heating the laminated body to sinter the joining material at a predetermined sintering temperature, in which the joining material satisfies the condition of the following Formula (I):
(M.sub.1−M.sub.2)/M.sub.1×100≥1.0  (I)
[in Formula (I), M.sub.1 represents a mass of the joining material when a temperature of the joining material reaches the sintering temperature in the second step, and M.sub.2 represents a non-volatile content in the joining material.]

A method of making an assembly can include juxtaposing a top surface of a first electrically conductive element at a first surface of a first substrate with a top surface of a second electrically conductive element at a major surface of a second substrate. One of: the top surface of the first conductive element can be recessed below the first surface, or the top surface of the second conductive element can be recessed below the major surface. Electrically conductive nanoparticles can be disposed between the top surfaces of the first and second conductive elements. The conductive nanoparticles can have long dimensions smaller than 100 nanometers. The method can also include elevating a temperature at least at interfaces of the juxtaposed first and second conductive elements to a joining temperature at which the conductive nanoparticles can cause metallurgical joints to form between the juxtaposed first and second conductive elements.

A semiconductor package includes a multilayer package substrate with a top layer including top filled vias through a top dielectric layer and top metal layer providing a top surface for leads and traces connected to the leads, and a bottom layer including bottom filled vias including contact pads through a bottom dielectric and metal layer. The top filled vias are for connecting the bottom and top metal layer. The bottom metal filled vias are for connecting the bottom metal layer to the contact pads. An integrated circuit (IC) die has nodes in its circuitry connected to the bond pads. The IC die is flipchip mounted onto the leads. A passive device(s) is surface mounted by an electrically conductive material on the top metal layer electrically connected between at least one adjacent pair of the leads. A mold compound is for encapsulating at least the IC die and passive device.