A semiconductor device is formed by providing a semiconductor die. A laser-assisted bonding (LAB) assembly is disposed over the semiconductor die. The LAB assembly includes an infrared (IR) camera. The IR camera is used to capture an image of the semiconductor die. Image processing is performed on the image to identify corners of the semiconductor die. Regions of interest (ROI) are identified in the image relative to the corners of the semiconductor die. Parameters can be used to control the size and location of the ROI relative to the respective corners. The ROI are monitored for temperature using the IR camera while LAB is performed.

An electronic component bonding machine is provided. The electronic component bonding machine includes: a support structure for supporting a substrate; a bond head assembly for holding an electronic component, and for bonding the electronic component to the substrate; and a measuring system for measuring a distance between (i) an upper target on the electronic component bonding machine and (ii) a lower target on the electronic component bonding machine, the upper target including at least one of a portion of the bond head assembly and the electronic component, the lower target including at least one of a portion of the support structure and the substrate.

A component mounting system for mounting a component on a substrate, the mounting system comprising a component supplying unit configured to supply the component; a substrate holding unit configured to hold the substrate in an orientation such that a mounting face for mounting the component on the substrate is facing vertically downward; a head configured to hold the component from vertically below; and a head drive unit that, by causing vertically upward movement of the head holding the component, causes the head to approach the substrate holding unit to mount the component on the mounting face of the substrate.

A manufacturing apparatus of a semiconductor device includes: a stage; a bonding head, including a mounting tool, a tool heater, and a lifting and lowering mechanism; and a controller performing bonding processing. The controller performs, in the bonding processing: first processing in which, after a chip is brought into contact with a substrate, as heating of the chip is started, the chip is pressurized against the substrate; distortion elimination processing in which, after the first processing and before melting of a bump, the lifting and lowering mechanism is driven in a lifting direction, thereby eliminating distortion of the bonding head; and second processing in which, after the distortion elimination processing, position control is performed on the lifting and lowering mechanism so as to cancel thermal expansion and contraction of the bonding head, thereby maintaining a gap amount at a specified target value.

An IC package including an integrated circuit die having a major surface and one or more solder bumps located on the major surface in at least one corner region of the major surface and a substrate having a surface, the surface including bump pads thereon. The major surface of the integrated circuit die faces the substrate surface, the one or more solder bumps are bonded to individual ones of the bump pads to thereby form a bond joint, the major surface of the integrated circuit die has a footprint area of at least about 400 mm.sup.2. A ratio of a coefficient of thermal expansion of the substrate (CTE.sub.sub) to a coefficient of thermal expansion of the integrated circuit die (CTE.sub.die) is at least about 3:1. A method of manufacturing an IC package is also disclosed.

A stacked device including a first substrate that includes a quantum information processing device, a second substrate bonded to the first substrate, and multiple bump bonds and at least one pillar between the first substrate and the second substrate. Each bump bond of the multiple bump bonds provides an electrical connection between the first substrate and the second substrate. At least one pillar defines a separation distance between a first surface of the first substrate and a first surface of the second substrate. A cross-sectional area of each pillar is greater than a cross-sectional area of each bump bond of the multiple bump bonds, where the cross-sectional area of each pillar and of each bump bond is defined along a plane parallel to the first surface of the first substrate or to the first surface of the second substrate.

Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.

A semiconductor device may include a first plate-like element having a first substantially planar connection surface with a first connection pad and a second plate-like element having a second substantially planar connection surface with a second connection pad corresponding to the first connection pad. The device may also include a connection electrically and physically coupling the first and second plate-like elements and arranged between the first and second connection pads. The connection may include a deformed elongate element arranged on the first connection pad and extending toward the second connection pad and solder in contact with the second connection pad and the elongate element.

An electronic device includes a first chip, a second chip bonded to the first chip with a bump, a first metal pattern provided on a first surface that is a surface of the first chip facing the second chip, and a second metal pattern provided on a second surface that is a surface of the second chip facing the first chip. The first chip has a first transmission region. A transmittance for light of the first transmission region is higher than a transmittance of a region other than the first transmission region in the first chip. The first metal pattern and the second metal pattern overlap the first transmission region in a thickness direction of the first chip and the second chip. The second metal pattern is located outside the first metal pattern in a direction in which the first surface and the second surface extend.

A display device may include: a substrate including a display area and a non-display area; and a pixel located in the display area, the pixel having an emission area and a pixel circuit area. The pixel may include: at least one transistor located in the pixel circuit area; a first pad electrode and a second pad electrode spaced from each other and located in the emission area, the first pad electrode and the second pad electrode being electrically connected to the at least one transistor; a first through hole penetrating one region of the first pad electrode; a second through hole penetrating one region of the second pad electrode; and a light emitting element located in the emission area, the light emitting element being electrically connected to the first pad electrode and the second pad electrode.