Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer, a die disposed in a cavity of the core layer, and an encapsulant disposed in the cavity between the die and a sidewall of the cavity. The package further includes a first patterned conductive layer disposed within the first dielectric layer, a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is between the device and the core layer, a second patterned conductive layer disposed within the second dielectric layer, and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is between the conductive pad and the core layer.

Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die having a conductive element and an antenna element over the semiconductor die. The chip package also includes a first conductive feature electrically connecting the conductive element of the semiconductor die and the antenna element. The chip package further includes a protective layer surrounding the first conductive feature. In addition, the chip package includes a second conductive feature over the first conductive feature. A portion of the second conductive feature is between the first conductive feature and the protective layer.

The present disclosure provides a packaged device that includes a first dielectric layer; a second dielectric layer, formed over the first dielectric layer, that includes a device substrate and a via extending from the first dielectric layer and through the second dielectric layer; and a third dielectric layer, formed over the second dielectric layer, that includes a conductive pillar extending through the third dielectric layer, wherein the conductive pillar is electrically coupled to the via of the second dielectric layer.

A chip packaging method and a chip packaging structure is disclosed. The method includes: attaching at least two chips to one side of substrate by adhesive layer, wherein device surface of the chip faces the substrate, and the substrate is provided therein with substrate wiring structure and/or chip; performing thinning treatment on the at least two chips provided on one side of the substrate, wherein the thinning treatment includes etching only the chips to reduce the thickness of the chips; plastically sealing the chips having undergone the thinning treatment to form a plastically sealed arrangement layer, and stacking at least two such plastically sealed arrangement layers on the substrate along plastic sealing direction; and punching the chips having undergone the thinning treatment to form first interconnection hole connecting the chips having undergone the thinning treatment to the substrate wiring structure, the chip in substrate, or the plastically sealed arrangement layer.

A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.

Sensor packages and manufacturing methods thereof are disclosed. One of the sensor packages includes a semiconductor chip and a redistribution layer structure. The semiconductor chip has a sensing surface. The redistribution layer structure is arranged to form an antenna transmitter structure aside the semiconductor chip and an antenna receiver structure over the sensing surface of the semiconductor chip.

A conductive structure, includes: a plurality of conductive layers; a plurality of conductive pillars being formed on the plurality of conductive layers, respectively; and a molding compound laterally coating the plurality of conductive pillars. Each of the plurality of conductive pillars is a taper-shaped conductive pillar, and is tapered from the conductive layers.

A conductive structure, a semiconductor package and methods of forming the same are disclosed. A conductive structure includes a metal feature, an insulating layer and a nitridized metal layer. The metal feature is disposed over a substrate and includes a lower metal pattern and an upper metal pattern over the lower metal pattern. The insulating layer surrounds the metal feature. The nitridized metal layer is disposed between the lower metal pattern and the upper metal pattern.

A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.

A nitride semiconductor device includes a semiconductor carrier, a first nitride-based chip, and first conformal connecting structures. The first nitride-based chip is disposed over the semiconductor carrier. The semiconductor carrier has a first planar surface. The first nitride-based chip has a second planar surface, first conductive pads, and first slanted surfaces. The first conductive pads are disposed in the second planar surface. The first slanted surfaces connect the second planar surface to the first planar surface. The first conformal connecting structures are disposed on the first planar surface and the first nitride-based chip. First obtuse angles are formed between the second planar surface and the first slanted surfaces. Each of the first conformal connecting structures covers one of the first slanted surfaces of the first nitride-based chip and one of the first obtuse angles and is electrically connected to the first conductive pads.