A semiconductor arrangement includes a lower semiconductor chip, an upper semiconductor chip arranged over an upper main side of the lower semiconductor chip, a metallization layer arranged on the upper main side of the lower semiconductor chip, and a bonding material which fastens the upper semiconductor chip on the lower semiconductor chip. The metallization layer includes a structure with increased roughness in comparison with the rest of the metallization layer, the structure being arranged along a contour of the upper semiconductor chip.

Present disclosure provides a semiconductor package, including a first substrate having a first active surface and a first trench recessed from the first active surface, a second substrate having a second trench facing the first trench, and a pathway cavity defined by the first trench and the second trench. The first trench comprises a first metal protrusion and a first insulating protrusion. A method for manufacturing the semiconductor package described herein is also disclosed.

A method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a plurality of conductive bumps on the plurality of pads correspondingly; disposing a solder bracing material surrounding the plurality of conductive bumps and over the surface of the substrate after the disposing of the plurality of conductive bumps, wherein the solder bracing material is in contact with a sidewall of each of the plurality of pads and the plurality of conductive bumps; disposing a release film on the solder bracing material and the plurality of conductive bumps; and removing the release film to form a rough surface of the solder bracing material. The rough surface of the solder bracing material includes a plurality of protruded portions and a plurality of recessed portions.

A semiconductor device package includes a semiconductor device, a non-semiconductor substrate over the semiconductor device, and a first connection element extending from the semiconductor device to the non-semiconductor substrate and electrically connecting the semiconductor device to the non-semiconductor substrate.

A method of manufacturing an image display device includes: providing a semiconductor growth substrate comprising a semiconductor layer; providing a circuit substrate comprising: a circuit element, a first wiring layer, and a first insulating film; forming a first metal layer that is located on the first insulating film and is electrically connected to the first wiring layer; bonding the semiconductor growth substrate to the circuit substrate and electrically connecting the first metal layer to the semiconductor layer; etching the semiconductor layer to form a light-emitting element; etching the first metal layer to form a plug electrically connected to the light-emitting element; forming a second insulating film covering the plug, the light-emitting element, and the first insulating film; removing a portion of the second insulating film to expose a light-emitting surface of the light-emitting element; and forming a second wiring layer electrically connected to the light-emitting surface.

A method for producing a semiconductor arrangement includes applying a metallization layer on an upper main side of a lower semiconductor chip, structuring the metallization layer, and fastening an upper semiconductor chip on the upper main side of the lower semiconductor chip by a bonding material, wherein the metallization layer is structured such that the metallization layer has an increased roughness along a contour of the upper semiconductor chip in comparison with the rest of the metallization layer, wherein wetting of the upper main side of the lower semiconductor chip by the bonding material is limited by a structure in the metallization layer to a region below the upper semiconductor chip.

A method of manufacturing a semiconductor device includes providing a substrate, disposing a plurality of pads on a surface of the substrate, disposing a plurality of conductive bumps on the plurality of pads correspondingly; disposing a solder bracing material surrounding the plurality of conductive bumps and over the surface of the substrate after the disposing of the plurality of conductive bumps, wherein the solder bracing material is in contact with a sidewall of each of the plurality of pads and the plurality of conductive bumps; disposing a release film on the solder bracing material and the plurality of conductive bumps; and removing the release film to form a rough surface of the solder bracing material. The rough surface of the solder bracing material includes a plurality of protruded portions and a plurality of recessed portions.

Present disclosure provides a semiconductor package, including a first substrate having a first active surface and a first trench recessed from the first active surface, a second substrate having a second trench facing the first trench, and a pathway cavity defined by the first trench and the second trench. The first trench comprises a first metal protrusion and a first insulating protrusion. A method for manufacturing the semiconductor package described herein is also disclosed.

A semiconductor device includes a first substrate including a plurality of first pads disposed on a first surface of the first substrate, a second substrate including a plurality of second pads disposed on a second surface of the substrate, a plurality of conductive bumps bonded the plurality of first pads with the plurality of second pads correspondingly, a solder bracing material disposed on the first surface and surrounded the plurality of conductive bumps, an underfill material surrounded the plurality of conductive bumps and disposed between the solder bracing material and the second surface, and a rough interface between the solder bracing material and the underfill material. The rough interface includes a plurality of protruded portions and a plurality of recessed portions.

A semiconductor arrangement includes a lower semiconductor chip, an upper semiconductor chip arranged over an upper main side of the lower semiconductor chip, a metallization layer arranged on the upper main side of the lower semiconductor chip, and a bonding material which fastens the upper semiconductor chip on the lower semiconductor chip. The metallization layer includes a structure with increased roughness in comparison with the rest of the metallization layer, the structure being arranged along a contour of the upper semiconductor chip.