Optical sensor modules and methods of fabrication are described. In an embodiment, an optical component is mounted on a module substrate. In an embodiment, a pillar of stacked wireballs adjacent the optical component is used for vertical connection between the module substrate and a top electrode pad of the optical component.

Optical sensor modules and methods of fabrication are described. In an embodiment, an optical component is mounted on a module substrate. In an embodiment, a pillar of stacked wireballs adjacent the optical component is used for vertical connection between the module substrate and a top electrode pad of the optical component.

The present disclosure provides a wafer-level chip scale packaging structure and a method for manufacturing the same. The method includes the following steps: 1) providing a first supporting substrate; 2) placing a first chip on the first supporting substrate, and forming a first packaging layer on the first chip; 3) separating the first chip and the surface of the first packaging layer in contact with the first chip from the first supporting substrate, and attaching the other surface of the first packaging layer to a second supporting substrate; 4) disposing a second packaging layer on the surface of the first packaging layer which is in contact with the first chip; 5) forming a rewiring layer on the second packing layer, the rewiring layer is electrically connected to the first chip; and 6) electrically connecting a second chip to the rewiring layer.

Optical sensor modules and methods of fabrication are described. In an embodiment, an optical component is mounted on a module substrate. In an embodiment, a pillar of stacked wireballs adjacent the optical component is used for vertical connection between the module substrate and a top electrode pad of the optical component.

Optical sensor modules and methods of fabrication are described. In an embodiment, an optical component is mounted on a module substrate. In an embodiment, a pillar of stacked wireballs adjacent the optical component is used for vertical connection between the module substrate and a top electrode pad of the optical component.

A method includes having a first wafer bonding recipe and a model of a wafer bonding process, the model comprising an input indicative of a physical parameter of a first wafer to be bonded to a second wafer and configured to output a wafer bonding recipe based on the physical parameter of the first wafer; obtaining measurements of the first wafer to obtain the physical parameter of the first wafer; generating, by the model, the first wafer bonding recipe based on the physical parameter of the first wafer; and bonding the first wafer to the second wafer in accordance with the first wafer bonding recipe to produce a first post-bond wafer.

The present disclosure provides a wafer-level chip scale packaging structure and a method for manufacturing the same. The method includes the following steps: 1) providing a first supporting substrate; 2) placing a first chip on the first supporting substrate, and forming a first packaging layer on the first chip; 3) separating the first chip and the surface of the first packaging layer in contact with the first chip from the first supporting substrate, and attaching the other surface of the first packaging layer to a second supporting substrate; 4) disposing a second packaging layer on the surface of the first packaging layer which is in contact with the first chip; 5) forming a rewiring layer on the second packing layer, the rewiring layer is electrically connected to the first chip; and 6) electrically connecting a second chip to the rewiring layer.

A method includes having a first wafer bonding recipe and a model of a wafer bonding process, the model comprising an input indicative of a physical parameter of a first wafer to be bonded to a second wafer and configured to output a wafer bonding recipe based on the physical parameter of the first wafer; obtaining measurements of the first wafer to obtain the physical parameter of the first wafer; generating, by the model, the first wafer bonding recipe based on the physical parameter of the first wafer; and bonding the first wafer to the second wafer in accordance with the first wafer bonding recipe to produce a first post-bond wafer.