A method is presented for fabricating a substrate comprised of a compound semiconductor. The method includes: growing a sacrificial layer onto a parent substrate; growing an epitaxial template layer on the sacrificial layer; removing the template layer from the parent substrate using an epitaxial lift-off procedure; and bonding the removed template layer to a host substrate using Van der Waals forces and thereby forming a compound semiconductor substrate.

The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.

A method is presented for fabricating a substrate comprised of a compound semiconductor. The method includes: growing a sacrificial layer onto a parent substrate; growing an epitaxial template layer on the sacrificial layer; removing the template layer from the parent substrate using an epitaxial lift-off procedure; and bonding the removed template layer to a host substrate using Van der Waals forces and thereby forming a compound semiconductor substrate.

The present technology relates to a semiconductor package. The semiconductor package comprises: a first component comprising a plurality of first dies stacked on top of each other, each of first dies comprising at least one side surface and an electrical contact exposed on the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies substantially coplanar with respect to each other to form a common sidewall; a first conductive pattern formed over the sidewall and at least partially spaced away from the sidewall, the first conductive pattern electrically interconnecting the electrical contacts of the plurality of first dies; at least one second component; and a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern formed over the sidewall of the first component.

A method for fabricating semiconductor device includes the steps of: providing a first wafer and a second wafer, bonding the first wafer onto a carrier by forming an adhesive layer between the carrier and the first wafer, conducting a front end of line (FEOL) process and a back end of line (BEOL) process on the first wafer and the second wafer, forming direct bond interconnects (DBI) on the first wafer and the second wafer, bonding the first wafer and the second wafer, and performing a de-bonding process to detach the carrier and the first wafer.