A method of removing a substrate, comprising: forming a growth restrict mask with a plurality of striped opening areas directly or indirectly upon a GaN-based substrate; and growing a plurality of semiconductor layers upon the GaN-based substrate using the growth restrict mask, such that the growth extends in a direction parallel to the striped opening areas of the growth restrict mask, and growth is stopped before the semiconductor layers coalesce, thereby resulting in island-like semiconductor layers. A device is processed for each of the island-like semiconductor layers. Etching is performed until at least a part of the growth restrict mask is exposed. The devices are then bonded to a support substrate. The GaN-based substrate is removed from the devices by a wet etching technique that at least partially dissolves the growth restrict mask. The GaN substrate that is removed then can be recycled.

A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.

A semiconductor device manufacturing method, including: a first treatment process for reducing an amount of oxygen and carbon adsorbed to a main surface of the conductive plate to 20 atomic % or less; a first checking process for checking whether the conductive plate has a temperature no higher than a reference temperature; a chip placement process for placing, responsive to the conductive plate having the temperature no higher than the reference temperature, a semiconductor chip on the main surface of the conductive plate via a sinter material; a first bonding process for applying heat and pressure to the sinter material according to a first condition that allows the organic substance to partially remain; a preparatory process for making preparations for further bonding the semiconductor chip; and a second bonding process for further applying heat and pressure to the sinter material according to a second condition that sinters the sinter material.

An arrangement for joining two joining members includes a first part having a support surface, a first carrier element configured to carry at least one foil, a transportation unit configured to arrange the first carrier element such that the foil is arranged above the support surface in a vertical direction, and a second part configured to exert pressure to a joining stack, when the joining stack is arranged on the support surface. The joining stack includes a first joining member arranged on the support surface, a second joining member, and an electrically conductive connection layer arranged between the joining members. When pressure is exerted on the joining stack, the foil is arranged between the second part and the joining stack and is pressed onto the joining stack and the joining stack is pressed onto the first part, compressing the connection layer and forming a bond between the joining members.

An arrangement for joining two joining members includes a first part having a support surface, a first carrier element configured to carry at least one foil, a transportation unit configured to arrange the first carrier element such that the foil is arranged above the support surface in a vertical direction, and a second part configured to exert pressure to a joining stack, when the joining stack is arranged on the support surface. The joining stack includes a first joining member arranged on the support surface, a second joining member, and an electrically conductive connection layer arranged between the joining members. When pressure is exerted on the joining stack, the foil is arranged between the second part and the joining stack and is pressed onto the joining stack and the joining stack is pressed onto the first part, compressing the connection layer and forming a bond between the joining members.

A device (2) is formed on a main surface of a substrate (1). The main surface of the substrate (1) is bonded to the undersurface of the counter substrate (14) via the bonding member (11,12,13) in a hollow state. A circuit (17) and a bump structure (26) are formed on the top surface of the counter substrate (14). The bump structure (26) is positioned in a region corresponding to at least the bonding member (11,12,13), and has a higher height than that of the circuit (17).

The present invention discloses a flexible integrated display panel module and manufacturing method thereof, the flexible integrated display panel module includes a flexible integrated display substrate, which including an integrated area, an active area and a non-display disposed at one side of the integrated area, the integrated area divided into a plurality of areas, used to defined as a corresponding functional area. The functional area includes: a display wiring functional area and a plurality of direct on-cell touch control wiring functional areas disposed on both sides of the display functional area.

A method of manufacturing a semiconductor device includes the following steps. A device wafer having a product-obtaining part and an edge part surrounding the product-obtaining part is provided. A passivation layer is formed to cover the device wafer. A first oxide cap layer is formed to cover the passivation layer. An edge trimming process is performed to polish an edge part of the first oxide cap layer, an edge part of the passivation layer and the edge part of the device wafer. A removing process is performed to remove the first oxide cap layer after the edge trimming process is performed. A second oxide cap layer is formed to cover the first oxide cap layer and the edge part of the device wafer.

Provided is a semiconductor device manufacturing method through which semiconductor elements are multilayered through the lamination of wafers in which the semiconductor elements are fabricated, the method thereof being suited for efficiently manufacturing semiconductor devices while realizing a large number of wafer lamination. With the method of the present invention, at least two wafer laminates are formed, each wafer laminate having a laminated structure, the structure including a plurality of wafers including an element forming surface and a back surface, with the element forming surface and the back surface facing between adjacent wafers; a through electrode is formed in each wafer laminate with the through electrode extending through an inside of the wafer laminate, from an element forming surface side of a first wafer located at one end of the wafer laminate in a lamination direction, to a position exceeding an element forming surface of a second wafer located at another end; the through electrode is exposed at a back surface side of the second wafer by grinding the back surface side thereof; and two wafer laminates that have been subjected to this exposing step are laminated and bonded while electrically connecting the through electrodes between the wafer laminates.

A method of soldering includes providing a substrate having a first metal joining surface, providing a semiconductor die having a second metal joining surface, providing a solder preform having a first interface surface and a second interface surface, arranging the solder preform between the substrate and the semiconductor die such that the first interface surface faces the first metal joining surface and such that the second interface surface faces the second metal joining surface, and performing a mechanical pressure-free diffusion soldering process that forms a soldered joint between the substrate and the semiconductor die by melting the solder preform and forming intermetallic phases in the solder. One or both of the first interface surface and the second interface surface has a varying surface profile that creates voids between the solder preform and one or both of the substrate and the semiconductor die before the melting of the solder preform.