A method comprises: providing a layer of curable adhesive material (4) on a substrate (2); forming a pattern of microstructures (321) on the layer of curable adhesive material (4); curing a first region (42) of the layer of curable adhesive material (4) at a first level and a second region (44) of the layer of curable adhesive material (4) at a second level greater than the first level; providing a solid circuit die (6) to directly attach to a major surface of the first region (42) of the layer of curable adhesive material (4); and further curing the first region (42) of the layer of curable adhesive material (4) to anchor the solid circuit die (6) on the first region (42) by forming an adhesive bond therebetween. The pattern of microstructures (321) may include one or more microchannels (321), the method further comprising forming one or more electrically conductive traces in the microchannels (321), in particular, by flow of a conductive particle containing liquid (8) by a capillary force and, optionally, under pressure. The at least one microchannel (321) may extend from the second region (44) to the first region (42) and have a portion beneath the solid circuit die (6). The solid circuit die (6) may have at least one edge disposed within a periphery of the first region (42) with a gap therebetween. The solid circuit die (6) may have at least one contact pad (72) on a bottom surface thereof, wherein the at least one contact pad (72) may be in direct contact with at least one of the electrically conductive traces in the microchannels (321). Forming the pattern of microstructures (321) may comprise contacting a major surface of a stamp (3) to the layer of curable adhesive material (4), the major surface having a pattern of raised features (32) thereon. The curable adhesive material (4) may be cured by an actinic light source such as an ultraviolet (UV) light source (7, 7′), wherein a mask may be provided to at least partially block the first region (42) of the layer of curable adhesive material (4) from the cure. The stamp (3) may be positioned in contact with the curable adhesive material (4) to replicate the pattern of raised features (32) to form the microstructures (321) while the curable adhesive material (4) is selectively cured by the actinic light source such as the ultraviolet (UV) light source (7). The first region (42) of the layer of curab

Embodiments of the present disclosure relate to methods of fabricating IC devices with IC structures with improved bonding between a semiconductor layer and a non-semiconductor support structure, as well as resulting IC devices, assemblies, and systems. An example method includes providing a semiconductor material over a semiconductor support structure and, subsequently, depositing a first bonding material on the semiconductor material. The method further includes depositing a second bonding material on a non-semiconductor support structure such as glass or mica wafers, followed by bonding the face of the semiconductor material with the first bonding material to the face of the non-semiconductor support structure with the second bonding material. Using first and second bonding materials that include silicon, nitrogen, and oxygen (e.g., silicon oxynitride or carbon-doped silicon oxynitride) may significantly improve bonding between semiconductor layers and non-semiconductor support structures compared to layer transfer techniques.

Embodiments of methods and apparatus for reducing warpage of a substrate are provided herein. In some embodiments, a method for reducing warpage of a substrate includes: applying an epoxy mold over a plurality of dies on the substrate in a dispenser tool; placing the substrate on a pedestal in a curing chamber, wherein the substrate has an expected post-cure deflection in a first direction; inducing a curvature on the substrate in a direction opposite the first direction; and curing the substrate by heating the substrate in the curing chamber.

A method includes bonding a III-V die directly to a Complementary Metal-Oxide-Semiconductor (CMOS) die to form a die stack. The III-V die includes a (111) semiconductor substrate, and a first circuit including a III-V based n-type transistor formed at a surface of the (111) semiconductor substrate. The CMOS die includes a (100) semiconductor substrate, and a second circuit including an n-type transistor and a p-type transistor on the (100) semiconductor substrate. The first circuit is electrically connected to the second circuit.

The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor wafers. In one aspect, a method for bonding a first semiconductor substrate to a second semiconductor substrate by direct bonding is described. The substrates are both provided on their contact surfaces with a dielectric layer, followed by a CMP step for reducing the roughness of the dielectric layer. Then a layer of SiCN is deposited onto the dielectric layer, followed by a CMP step which reduces the roughness of the SiCN layer to the order of 1 tenth of a nanometer. Then the substrates are subjected to a pre-bond annealing step and then bonded by direct bonding, possibly preceded by one or more pre-treatments of the contact surfaces, and followed by a post-bond annealing step, at a temperature of less than or equal to 250° C. It has been found that the bond strength is excellent, even at the above named annealing temperatures, which are lower than presently known in the art.

A printed circuit film includes: a base film including a first film portion extending in a first direction, a second film portion extending in the first direction, and a third film portion extending in the first direction; a plurality of lead wires extending in the second direction and disposed on the first, second, and third film portions, the plurality of lead wires being spaced apart from each other in the first direction; and a bonding member including: a conductive member disposed to overlap the plurality of lead wires on the first film portion; a first non-conductive member disposed to overlap the plurality of lead wires and the second film portion; and a second non-conductive member disposed to overlap the plurality of lead wires and the third film portion, wherein the conductive member is disposed between the first non-conductive member and the second non-conductive member in the second direction.

A display module includes: a substrate; a side wiring extending along a side surface of the substrate, the side wiring electrically connecting a TFT layer of the substrate at a first end of the side wiring with a rear wiring layer of the substrate at a second end of the side wiring; a front cover disposed on and bonded with a mounting surface of the substrate; a metal plate disposed on and bonded with the rear surface; a side cover covering the side wiring and the side surface; a waterproof member configured to seal the second end of the side wiring from outside and prevent moisture permeation; and a side end member disposed on and covering the side cover and the waterproof member, and the side end member being grounded to the metal plate.

The present invention discloses a method for preparing a semiconductor sample for failure analysis, which is characterized by using an adhesive layer comprising a non-volatile and non-liquid adhesive material with higher adhesion to the dielectric materials and lower adhesion to the metallic contact materials to selectively remove part of the dielectric materials in a large area with high uniformity, but completely remain the metallic contact materials, and not chemically react with the semiconductor specimens or even damage to the structures of interest to be analyzed, and different adhesive materials can be selected as the adhesive layer to control the adhesion to the dielectric layer, thereby the removed thickness of the dielectric layer can be controlled to provide a semiconductor specimen for failure analysis.

A printed circuit film includes: a base film including a first film portion extending in a first direction, a second film portion extending in the first direction, and a third film portion extending in the first direction; a plurality of lead wires extending in the second direction and disposed on the first, second, and third film portions, the plurality of lead wires being spaced apart from each other in the first direction; and a bonding member including: a conductive member disposed to overlap the plurality of lead wires on the first film portion; a first non-conductive member disposed to overlap the plurality of lead wires and the second film portion; and a second non-conductive member disposed to overlap the plurality of lead wires and the third film portion, wherein the conductive member is disposed between the first non-conductive member and the second non-conductive member in the second direction.

A method of fabricating a printed circuit film including the steps of preparing a base film, and a plurality of lead wires disposed on the base film, the plurality of lead wires spaced apart from each other in a first direction and extending in a second direction intersecting the first direction, and forming a bonding member including a conductive member disposed to overlap a central portion of each of the plurality of lead wires, a first non-conductive member disposed to overlap a first portion of the plurality of lead wires in the second direction, and a second non-conductive member disposed to overlap a second portion of the plurality of lead wires in the second direction.