Panel level packaging (PLP) with high accuracy and high scalability is disclosed. The PLP employs an alignment carrier with a low coefficient of expansion which is configured with die regions having local die alignment marks. For example, local die alignment marks are provided for each die attach region. Depending on the size of the panel, it may be segmented into blocks, each with die regions with local die alignment marks. In addition, a block includes an alignment die region configured for attaching an alignment die. Linear and non-linear positional errors are reduced due to local die alignment marks and alignment dies. The use of local die alignment marks and alignment dies results in increase yields as well as scaling, thereby improving throughput and decreasing overall costs.

A tiled light emitting diode (LED) display panel includes multiple flexible back plates arranged in tiles. Each flexible back plate has multiple through holes formed thereon. A pixel array is formed by multiple LEDs on the flexible back plates and collectively defines multiple pixels. Each pixel includes one LED and thin-film transistor (TFT) circuits disposed on a first side of a corresponding flexible back plate. A printed circuit board (PCB) is disposed at a second side of the flexible back plates. A third side of the PCB faces the second side of the flexible back plates and has multiple signal lines formed thereon. The LEDs and the TFT circuits of the pixels are electrically connected to the corresponding signal lines via multiple conductive structures formed in the through holes. A resistance per unit length of each flexible back plates is greater than a resistance per unit length of the PCB.

A tiled light emitting diode (LED) display panel includes multiple flexible back plates arranged in tiles. Each flexible back plate has multiple through holes formed thereon. A pixel array is formed by multiple LEDs on the flexible back plates and collectively defines multiple pixels. Each pixel includes one LED and thin-film transistor (TFT) circuits disposed on a first side of a corresponding flexible back plate. A printed circuit board (PCB) is disposed at a second side of the flexible back plates. A third side of the PCB faces the second side of the flexible back plates and has multiple signal lines formed thereon. The LEDs and the TFT circuits of the pixels are electrically connected to the corresponding signal lines via multiple conductive structures formed in the through holes. A resistance per unit length of each flexible back plates is greater than a resistance per unit length of the PCB.

Panel level packaging (PLP) with high accuracy and high scalability is disclosed. The PLP employs an alignment carrier with a low coefficient of expansion which is configured with die regions having local die alignment marks. For example, local die alignment marks are provided for each die attach region. Depending on the size of the panel, it may be segmented into blocks, each with die regions with local die alignment marks. In addition, a block includes an alignment die region configured for attaching an alignment die. Linear and non-linear positional errors are reduced due to local die alignment marks and alignment dies. The use of local die alignment marks and alignment dies results in increase yields as well as scaling, thereby improving throughput and decreasing overall costs.

A conductive connecting member formed on a bonded face of an electrode terminal of a semiconductor or an electrode terminal of a circuit board, the conductive connecting member comprising a porous body formed in such manner that a conductive paste containing metal fine particles (P) having mean primary particle diameter from 10 to 500 nm and an organic solvent (S), or a conductive paste containing the metal fine particles (P) and an organic dispersion medium (D) comprising the organic solvent (S) and an organic binder (R) is heating-treated so as for the metal fine particles (P) to be bonded, the porous body being formed by bonded metal fine particles (P) having mean primary particle diameter from 10 to 500 nm, a porosity thereof being from 5 to 35 volume %, and mean pore diameter being from 1 to 200 nm.

The invention concerns a method of flip-chip assembly between first (1) and second (2) components each comprising connection pads (11, 21) on one of the faces of same, referred to as assembly faces, which involves transferring the components onto each other via the assembly faces of same in such a way as to create electrical interconnections between the pads of the first and second components. The invention involves transforming the copper oxide into copper by UV annealing, very locally, in the gap between the components, at least around the areas adjacent to the connection pads. The method according to the invention can be used for any component that is transparent to UV rays, including for substrates made from a plastic material such as substrates made from PEN or PET. The invention also concerns the assembly of two components obtained by the method.