A semiconductor device includes a semiconductor die, an electrical contact arranged on a surface of the semiconductor die, and a metal layer arranged on the electrical contact, wherein the metal layer includes a singulated part of at least one of a metal foil, a metal sheet, a metal leadframe, or a metal plate. When viewed in a direction perpendicular to the surface of the semiconductor die, a footprint of the electrical contact and a footprint of the metal layer are substantially congruent.

An array substrate includes a glass substrate GS, an alignment mark 29, and first traces 19. The glass substrate GS has a corner portion 30 having an outline defined by a first edge portion 11b1 and a second edge portion 11b2 crossing the first edge portion 11b1. The alignment mark 29 is disposed at the corner portion 30 and used as the positioning index in mounting a driver 21 and a flexible printed circuit board 13. The alignment mark 29 at least includes first and second side portions 29a, 29b parallel to the first and second edge portions 11b1, 11b2, respectively. One end of the second side portion 29b is continuous to one end of the first side portion 29a. The alignment mark 29 has an outline that is on a same plane with a reference line BL connecting other ends of the first side portion 29a and the second side portion 29b linearly. The first traces 19 include inclined portions 31 that are inclined with respect to the first and second side portions 29a, 29b along the reference line BL.

A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.

A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The semiconductor package structure includes a first passivation layer, a first metal layer and a first semiconductor die. The first metal layer is embedded in the first passivation layer. The first metal layer defines a first through-hole. The first semiconductor die is disposed on the first passivation layer.

A package includes a semiconductor carrier, a first die, a second die, a first encapsulant, a second encapsulant, and an electron transmission path. The first die is disposed over the semiconductor carrier. The second die is stacked on the first die. The first encapsulant laterally encapsulates the first die. The second encapsulant laterally encapsulates the second die. The electron transmission path is electrically connected to a ground voltage. A first portion of the electron transmission path is embedded in the semiconductor carrier, a second portion of the electron transmission path is aside the first die and penetrates through the first encapsulant, and a third portion of the electron transmission path is aside the second die and penetrates through the second encapsulant.

A method and an apparatus for bonding semiconductor substrates are provided. The apparatus includes a first support configured to carry a first semiconductor substrate and a second semiconductor substrate bonded to each other, a gauging component embedded in the first support and comprising a fiducial pattern, and a first sensor disposed proximate to the gauging component, and configured to emit a light source towards the fiducial pattern of the gauging component.

Panel level packaging (PLP) with high accuracy and high scalability is disclosed. The PLP includes dies bonded face down onto an alignment carrier configured with die bond regions. Pre-bond and post bond inspection are performed at the carrier level to ensure accurate bonding of the dies to the carrier.

A mounting apparatus for stacking and mounting two or more semiconductor chips at a plurality of locations on a substrate includes: a first mounting head for forming, at a plurality of locations on the substrate, temporarily stacked bodies in which two or more semiconductor chips are stacked in a temporarily press-attached state; and a second mounting head for forming chip stacked bodies by sequentially finally press-attaching the temporarily stacked bodies formed at the plurality of locations. The second mounting head includes: a press-attaching tool for heating and pressing an upper surface of a target temporarily stacked body to thereby finally press-attach the two or more semiconductor chips configuring the temporarily stacked body altogether; and one or more heat-dissipation tools having a heat-dissipating body which, by coming into contact with an upper surface of another stacked body positioned around the target temporarily stacked body, dissipates heat from the another stacked body.

The present invention includes: a position detection unit (55) detecting positions of semiconductor chips and storing each detected position in a position database (56); a position correction unit (57) outputting a corrected bonding position; and a bonding control unit (58) performing bonding of the semiconductor chips based on the corrected bonding position input from the position correction unit (57). The position correction unit (57) calculates position shift amounts between the semiconductor chips of respective stages and an accumulated position shift amount, and when the accumulated position shift amount is greater than or equal to a predetermined threshold value, corrects the position of the semiconductor chip by the accumulated position shift amount and outputs it as the corrected bonding position, and the bonding control unit (58) performs bonding of the semiconductor chip of the next stage at the corrected bonding position input from the position correction unit.

An electronic device includes a substrate, and the substrate may include one or more layers. The one or more layers may include a dielectric material and may include one or more electrical traces. The electronic device may include a layer of conductive material, and the layer of conductive material may define a void in the conductive material. The electronic device may include a fiducial mark, and the fiducial mark may include a filler material positioned in the void defined by the conductive material. The fiducial mark may be coupled to the layer of conductive material. The filler material may have a lower reflectivity in comparison to the conductive material, for instance to provide a contrast with the conductive material.