A semiconductor device according to the present invention includes a semiconductor chip, an electrode pad made of a metal material containing aluminum and formed on a top surface of the semiconductor chip, an electrode lead disposed at a periphery of the semiconductor chip, a bonding wire having a linearly-extending main body portion and having a pad bond portion and a lead bond portion formed at respective ends of the main body portion and respectively bonded to the electrode pad and the electrode lead, and a resin package sealing the semiconductor chip, the electrode lead, and the bonding wire, the bonding wire is made of copper, and the entire electrode pad and the entire pad bond portion are integrally covered by a water-impermeable film.

According to one embodiment, a method of manufacturing a semiconductor device includes forming a metal bump on a first surface side of a semiconductor chip, positioning the semiconductor chip so the metal bump contacts a pad of an interconnection substrate, and applying a first light from a second surface side of the semiconductor chip and melting the metal bump with the first light. After the melting, the melted metal bump is allowed to resolidify by stopping or reducing the application of the first light. The semiconductor chip is then pressed toward the interconnection substrate. A second light is then applied from the second surface side of the semiconductor chip while the semiconductor chip is being pressed toward the interconnection substrate to melt the metal bump. After the melting, the melted metal bump is allowed to resolidify by the stopping or reducing of the application of the second light.

A semiconductor package includes a package substrate, a processor chip mounted on the package substrate, a first stack structure on the package substrate, the first stack structure including a number M of memory chips stacked on the processor chip, and a second stack structure on the package substrate and spaced apart from the processor chip, the second stack structure including a number N of memory chips stacked on the package substrate. A number Q of channels that electrically connect the memory chips of the second stack structure with the processor chip may be greater than a number P of channels that electrically connect the memory chips of the first stack structure with the processor chip, or the number N of memory chips included in the second stack structure may be greater than the number M of memory chips included in the first stack structure.

Disclosed is a semiconductor package comprising a first chip stack including on a substrate a plurality of first semiconductor chips in an offset stack structure and stacked to expose a connection region at a top surface of each of the first semiconductor chips, a second semiconductor chip on the substrate and horizontally spaced apart from the first chip stack, a spacer on the second semiconductor chip, and a second chip stack including third semiconductor chips in an offset stack structure on the first chip stack and the spacer. Each of the first semiconductor chips includes a first chip pad on the connection region and a first wire that extends between the first chip pad and the substrate. The first wire of an uppermost one of the first semiconductor chips is horizontally spaced apart from a lowermost one of the third semiconductor chips.

An electronic device is provided, the electronic device includes a driving substrate, the driving substrate includes a plurality of first grooves and a plurality of second grooves, the first grooves and the second grooves have different sizes, at least one first electronic component of the plurality of first electronic components is disposed in one of the plurality of first grooves, at least one second electronic component of the plurality of second electronic components is disposed in one of the plurality of second grooves, a maximum length passing through a center of a bottom surface of the at least one first electronic component is defined as L1, a bottom length of one side of at least one second groove among the second grooves is defined as L2, and the at least one first electronic component and the at least one second groove satisfy the condition of L1>L2.

A semiconductor device includes a first semiconductor chip having a first surface and a second surface; a first adhesive layer on the first surface; a second semiconductor chip that includes a third surface and a fourth surface, and a connection bump on the third surface. The connection bump is coupled to the first adhesive layer. The semiconductor device includes a wiring substrate connected to the connection bump. The semiconductor device includes a first resin layer covering the connection bump between the second semiconductor chip and the wiring substrate, and covers one side surface of the second semiconductor chip connecting the third surface and the fourth surface. The first adhesive layer covers an upper portion of the at least one side surface. The first resin layer covers a lower portion of the t least one side surface. The first adhesive layer and the first resin layer contact each other.

A semiconductor device includes: a substrate; a semiconductor element arranged on the substrate; a plate-like member electrically connected to the semiconductor element; a first electrode formed on the semiconductor element and joined to the plate-like member with solder; a second electrode formed on the semiconductor element and spaced from the first electrode, and including a metal capable of forming an alloy with the solder; and a metal film formed on the semiconductor element and spaced from the second electrode in a region on the first electrode side as seen from the second electrode, in a two-dimensional view of the semiconductor element as seen from the plate-like member, and including a metal capable of forming an alloy with the solder.

An electronic apparatus including a substrate, a plurality of first bonding pads, an electronic device, and a first spacer is provided. The first bonding pads are disposed on the substrate. The electronic device is disposed on the substrate and electrically connected to the first bonding pads. The first spacer is disposed between the electronic device and the substrate. The electronic device is capable of effectively controlling a height and uniformity of a gap between the electronic device and the substrate, so as to prevent the electronic device from being tilted and ensure the electronic device to have a favorable structural reliability.

A semiconductor package for effectively arranging devices in a limited space is provided. The semiconductor package includes: a substrate; a semiconductor chip formed on the substrate, the semiconductor chip including a center area, a first edge area, which is disposed on a first side of the center area with respect to a first directional axis, and a second edge area, which is disposed on a second side of the center area opposite the first side with respect to the first directional axis; a first spacer formed on the substrate and spaced apart from the semiconductor chip in a direction along the first directional axis; a second spacer formed on the substrate and spaced apart from the semiconductor chip in a direction along the first directional axis; a first chip stack disposed on the semiconductor chip and the first spacer; and a second chip stack disposed on the semiconductor chip and the second spacer. A lowermost chip of the first chip stack is positioned on the first edge area of the semiconductor chip, but not on the center area of the semiconductor chip, and a lowermost chip of the second chip stack is positioned on the second edge area of the semiconductor chip, but not on the center area of the semiconductor chip.

A semiconductor package includes a package substrate, a semiconductor chip on the package substrate, the semiconductor chip including a logic chip and a memory stack structure on the logic chip, a connector and a connector terminal below the package substrate, a molding layer that covers the semiconductor chip, the molding layer having a recess region on a top surface of the molding layer, a housing that covers the molding layer, and an air gap on the semiconductor chip, the air gap being defined by the housing and the recess region of the molding layer, and the molding layer separating the air gap from the memory stack structure of the semiconductor chip.