Underfill materials with graded moduli for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, the underfill material between a semiconductor die and a package substrate includes a matrix material, first filler particles with a first size distribution, and second filler particles with a second size distribution different than the first size distribution. Centrifugal force may be applied to the underfill material to arrange the first and second filler particles such that the underfill material may form a first region having a first elastic modulus and a second region having a second elastic modulus different than the first elastic modulus. Once the underfill material is cured, portions of conductive pillars coupling the semiconductor die with the package substrate may be surrounded by the first region, and conductive pads of the package substrate may be surrounded by the second region.

Underfill materials with graded moduli for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, the underfill material between a semiconductor die and a package substrate includes a matrix material, first filler particles with a first size distribution, and second filler particles with a second size distribution different than the first size distribution. Centrifugal force may be applied to the underfill material to arrange the first and second filler particles such that the underfill material may form a first region having a first elastic modulus and a second region having a second elastic modulus different than the first elastic modulus. Once the underfill material is cured, portions of conductive pillars coupling the semiconductor die with the package substrate may be surrounded by the first region, and conductive pads of the package substrate may be surrounded by the second region.

Underfill materials with graded moduli for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, the underfill material between a semiconductor die and a package substrate includes a matrix material, first filler particles with a first size distribution, and second filler particles with a second size distribution different than the first size distribution. Centrifugal force may be applied to the underfill material to arrange the first and second filler particles such that the underfill material may form a first region having a first elastic modulus and a second region having a second elastic modulus different than the first elastic modulus. Once the underfill material is cured, portions of conductive pillars coupling the semiconductor die with the package substrate may be surrounded by the first region, and conductive pads of the package substrate may be surrounded by the second region.

Underfill materials with graded moduli for semiconductor device assemblies, and associated methods and systems are disclosed. In one embodiment, the underfill material between a semiconductor die and a package substrate includes a matrix material, first filler particles with a first size distribution, and second filler particles with a second size distribution different than the first size distribution. Centrifugal force may be applied to the underfill material to arrange the first and second filler particles such that the underfill material may form a first region having a first elastic modulus and a second region having a second elastic modulus different than the first elastic modulus. Once the underfill material is cured, portions of conductive pillars coupling the semiconductor die with the package substrate may be surrounded by the first region, and conductive pads of the package substrate may be surrounded by the second region.

According to one embodiment, a controller is configured to calculate a matching rate of grid shapes between each semiconductor wafer of a first semiconductor wafer group and each semiconductor wafer of a second semiconductor wafer group, and generate pairing information, into which combinations of semiconductor wafers used in calculation of matching rates are registered when the matching rates fall within a predetermined range. Further, the controller is configured to select a first semiconductor wafer to be held by a first semiconductor wafer holder from the first semiconductor wafer group, and select a second semiconductor wafer from semiconductor wafers of the second semiconductor wafer group, which are paired with the first semiconductor wafer, with reference to the pairing information.

According to one embodiment, a controller is configured to calculate a matching rate of grid shapes between each semiconductor wafer of a first semiconductor wafer group and each semiconductor wafer of a second semiconductor wafer group, and generate pairing information, into which combinations of semiconductor wafers used in calculation of matching rates are registered when the matching rates fall within a predetermined range. Further, the controller is configured to select a first semiconductor wafer to be held by a first semiconductor wafer holder from the first semiconductor wafer group, and select a second semiconductor wafer from semiconductor wafers of the second semiconductor wafer group, which are paired with the first semiconductor wafer, with reference to the pairing information.