A sintered member is provided between a semiconductor chip and a terminal. The sintered member is made of a sinter sheet by heating and pressing the same. The semiconductor chip is connected to the terminal via the sintered member. Convex portions are formed at a front-side surface of the semiconductor chip. Concave portions, each of which has such a shape corresponding to that of each convex portion of the semiconductor chip, are formed at a surface of the sintered member facing to the semiconductor chip.

Disclosed herein is a semiconductor device, including: a first substrate including a first electrode, and a first insulating film configured from a diffusion preventing material for the first electrode and covering a periphery of the first electrode, the first electrode and the first insulating film cooperating with each other to configure a bonding face; and a second substrate bonded to and provided on the first substrate and including a second electrode joined to the first electrode, and a second insulating film configured from a diffusion preventing material for the second electrode and covering a periphery of the second electrode, the second electrode and the second insulating film cooperating with each other to configure a bonding face to the first substrate.

Disclosed herein is an electrical connecting structure having nano-twins copper, including a first substrate having a first nano-twins copper layer and a second substrate having a second nano-twins copper layer. The first nano-twins copper layer includes a plurality of first nano-twins copper grains. The second nano-twins copper layer includes a plurality of second nano-twins copper grains. The first nano-twins copper layer is joined with the second nano-twins copper layer. At least a portion of the first nano-twins copper grains extend into the second nano-twins copper layer, or at least a portion of the second nano-twins copper grains extend into the first nano-twins copper layer.

This disclosure relates to a cascode HEMT semiconductor device including a lead frame, a die pad attached to the lead frame, and a HEMT die attached to the die pad. The HEMT die includes a HEMT source and a HEMT drain on a first side, and a HEMT gate on a second side. The device further includes a MOSFET die attached to the source of the HEMT die, and the MOSFET die includes a MOSFET source, a MOSFET gate and a MOSFET drain. The MOSFET drain is connected to the HEMT source, and the MOSFET source includes a MOSFET source clip. The MOSFET source clip includes a pillar so to connect the MOSFET source to the HEMT gate, and the connection between the MOSFET source to the HEMT gate is established by a conductive material.

An array substrate includes connecting leads, a signal channel region extending in a first direction, a first power voltage lead, and a second power voltage lead. Any one of the signal channel region includes at least two control region columns extending in the first direction, and any one of the control region columns includes a plurality of control regions arranged along the first direction. Any one of the control regions includes a pad connecting circuit and a first pad group for bonding a microchip, the first pad group is electrically connected to the first power voltage lead. The pad connection circuit includes a plurality of second pad groups, and is provided with a first end electrically connected to the first pad group, and a second end electrically connected to the second power voltage lead.

A method of manufacturing a cascode HEMT semiconductor device including a lead frame, a die pad with an indentation attached to the lead frame, and a HEMT die attached to the die pad. The HEMT die includes a HEMT source and a HEMT drain on a first side, and a HEMT gate on a second side. The device further includes a MOSFET die attached to the source of the HEMT die, and the MOSFET die includes a MOSFET source, a MOSFET gate and a MOSFET drain. The MOSFET drain is connected to the HEMT source, and the MOSFET source includes a MOSFET source clip. The MOSFET source clip includes a pillar so to connect the MOSFET source to the HEMT gate, and the connection between the MOSFET source to the HEMT gate is established by a conductive material.

An anisotropic conductive film includes a conductive layer; a first resin insulating layer over a first surface of the conductive layer; and a second resin insulating layer over a second surface of the conductive layer, wherein the conductive layer comprises a plurality of conductive particles and a nano fiber connecting the plurality of conductive particles to each other, each of the plurality of conductive particles comprising a plurality of needle-shaped protrusions having a conical shape, and wherein the first resin insulating layer and the second resin insulating layer comprise a same material and have different thicknesses.

An anisotropic conductive film includes a conductive layer; a first resin insulating layer over a first surface of the conductive layer; and a second resin insulating layer over a second surface of the conductive layer, wherein the conductive layer comprises a plurality of conductive particles and a nano fiber connecting the plurality of conductive particles to each other, each of the plurality of conductive particles comprising a plurality of needle-shaped protrusions having a conical shape, and wherein the first resin insulating layer and the second resin insulating layer comprise a same material and have different thicknesses.

A semiconductor device includes a first semiconductor layer, a first metal layer, a bonding layer, a second metal layer, and a second semiconductor layer. The first metal layer is located on the first semiconductor layer and is in contact with the first semiconductor layer. The bonding layer is located on the first metal layer and is in contact with the first metal layer. The bonding layer is conductive. The second metal layer is located on the bonding layer and is in contact with the bonding layer. The second semiconductor layer is located on the second metal layer and is in contact with the second metal layer. The second semiconductor layer includes at least a portion of a semiconductor element.

Disclosed herein is an electrical connecting structure having nano-twins copper, including a first substrate having a first nano-twins copper layer and a second substrate having a second nano-twins copper layer. The first nano-twins copper layer includes a plurality of first nano-twins copper grains. The second nano-twins copper layer includes a plurality of second nano-twins copper grains. The first nano-twins copper layer is joined with the second nano-twins copper layer. At least a portion of the first nano-twins copper grains extend into the second nano-twins copper layer, or at least a portion of the second nano-twins copper grains extend into the first nano-twins copper layer.