Patent classifications
H
ELECTRICITY
Load children
H01
ELECTRIC ELEMENTS
Load children
H01L
SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
Load children
2224/00
Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/80
Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/8338
Bonding interfaces outside the semiconductor or solid-state body
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/83498
with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/836
with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/83638
the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
Load children Filter patents View analytics View as hierarchy Open in page
H01L2224/83657
Cobalt [Co] as principal constituent
Filter patents View analytics View as hierarchy Open in page

H01L2224/83657

Method and apparatus for forming contacts on an integrated circuit die using a catalytic adhesive
10685931 · 2020-06-16 · ·

A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.

Method and Apparatus for forming Contacts on an Integrated Circuit Die using a Catalytic Adhesive
20180158793 · 2018-06-07 · ·

A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.

Integrated circuit wafer integration with catalytic laminate or adhesive
09922951 · 2018-03-20 · ·

A catalytic laminate is formed from a resin, a fiber reinforced layer, and catalytic particles such that the catalytic particles are disposed throughout the catalytic laminate but excluded from the outer surface of the catalytic laminate. The catalytic laminate has trace channels and vias formed to make a single or multi-layer catalytic laminate printed circuit board. Apertures with locations which match the locations of integrated circuit pads are formed in the laminate PCB. The integrated circuit is bonded to the catalytic laminate PCB, and the integrated circuit and laminate are both subjected to electroless plating, thereby electrically connecting the integrated circuit to the single or multi-layer catalytic laminate PCB.