A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

A high voltage semiconductor package includes a semiconductor device. The semiconductor device includes a high voltage semiconductor transistor chip having a front side and a backside. A low voltage load electrode and a control electrode are disposed on the front side of the semiconductor transistor chip. A high voltage load electrode is disposed on the backside of the semiconductor transistor chip. The semiconductor package further includes a dielectric inorganic substrate. The dielectric inorganic substrate includes a pattern of first metal structures running through the dielectric inorganic substrate and connected to the low voltage load electrode, and at least one second metal structure running through the dielectric inorganic substrate and connected to the control electrode. The front side of the semiconductor transistor chip is attached to the dielectric inorganic substrate by a wafer bond connection, and the dielectric inorganic substrate has a thickness of at least 50 μm.

A package structure includes a substrate, a plurality of conductive pads, a light-emitting diode, a photo imageable dielectric material, and a black matrix. The substrate includes a top surface. The conductive pads are located on the top surface of the substrate. The light-emitting diode is located on the conductive pads. The photo imageable dielectric material is located between the light-emitting diode and the top surface of the substrate and between the conductive pads. An orthogonal projection of the light-emitting diode on the substrate is overlapped with an orthogonal projection of the photo imageable dielectric material on the substrate. The black matrix is located on the top surface of the substrate and the conductive pads.

A semiconductor device having an integrated antenna is provided. The semiconductor device includes a base die having an integrated circuit formed at an active surface and a cap die bonded to the backside surface of the base die. A metal trace is formed over a top surface of the cap die. A cavity is formed under the metal trace. A conductive via is formed through the base die and the cap die interconnecting the metal trace and a conductive trace of the integrated circuit.

A semiconductor device having an integrated antenna is provided. The semiconductor device includes a base die having an integrated circuit formed at an active surface and a cap die bonded to the backside surface of the base die. A metal trace is formed over a top surface of the cap die. A cavity is formed under the metal trace. A conductive via is formed through the base die and the cap die interconnecting the metal trace and a conductive trace of the integrated circuit.

A wire bonding method includes bonding a tip of a wire provided through a clamp and a capillary onto a bonding pad of a chip, moving the capillary to a connection pad of a substrate corresponding to the bonding pad, bonding the wire to the connection pad to form a bonding wire connecting the bonding pad to the connection pad, before the capillary is raised from the connection pad, applying a electrical signal to the wire to detect whether the wire and the connection pad are in contact with each other, changing a state of the clamp to a closed state when the wire is not in contact with the connection pad and maintaining the state of the clamp in an open state when the wire is in contact with the connection pad, and raising the capillary from the connection pad while maintaining the state of the clamp.

A semiconductor package includes a first connection structure, a first semiconductor chip on an upper surface of the first connection structure, a first molding layer on the upper surface of the first connection structure and surrounding the first semiconductor chip, a first bond pad on the first semiconductor chip, a first bond insulation layer on the first semiconductor chip and the first molding layer and surrounding the first bond pad, a second bond pad directly contacting the first bond pad, a second bond insulation layer surrounding the second bond pad; and a second semiconductor chip on the second bond pad and the second bond insulation layer.

A semiconductor package includes a semiconductor subassembly disposed on a package substrate and including: a first layer including first dies, and an encapsulation material encapsulating the first dies; a second layer adjacent the first layer and including a substrate; a solid component disposed on the first layer; and an interface layer disposed between and mechanically bonding the solid component and the first layer. The interface layer provides a direct dielectric-to-dielectric bond including a first dielectric sublayer directly adjacent the first layer, and a second dielectric sublayer directly adjacent the first dielectric sublayer and including an amorphous material. Second dies may be disposed on the package substrate adjacent the semiconductor subassembly. A heat spreader is disposed over the semiconductor subassembly and the second dies; and a TIM is coupled to the heat spreader at one side thereof, and to respective ones of the semiconductor subassembly and the one or more dies at another side thereof.

A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing a wafer stack with first and second wafers bonded together. The wafers include edge and non-edge regions, and at least one of the first and second wafers includes devices formed in the non-edge region. The first wafer serves as the base wafer while the second wafer serves as the top wafer of the wafer stack, where the base wafer is wider than the top wafer, providing a step edge of the wafer stack. An edge protection seal is formed on the wafer stack, where first and second layers are deposited on the wafer stack including at the top wafer and step edge of the wafer stack. The portion of the first and second layers on the step edge of the wafer stack forms the edge protection seal which protects the devices in the wafer stack in subsequent processing.

A semiconductor wafer stack and a method of forming a semiconductor device is disclosed. The method includes providing a wafer stack with first and second wafers bonded together. The wafers include edge and non-edge regions, and at least one of the first and second wafers includes devices formed in the non-edge region. The first wafer serves as the base wafer while the second wafer serves as the top wafer of the wafer stack, where the base wafer is wider than the top wafer, providing a step edge of the wafer stack. An edge protection seal is formed on the wafer stack, where first and second layers are deposited on the wafer stack including at the top wafer and step edge of the wafer stack. The portion of the first and second layers on the step edge of the wafer stack forms the edge protection seal which protects the devices in the wafer stack in subsequent processing.