Provided is a method that allows for firm joining of power module components even if a joining area is large. The method includes: forming an oxygen ion conductor layer on a surface of one of a first member to be joined containing metal and a second member to be joined containing ceramic; arranging the first member to be joined and the second member to be joined so that they are in contact with each other via the oxygen ion conductor layer; connecting the first member to be joined to one of a positive electrode side and a negative electrode side of a voltage application device and the second member to be joined to the other; and applying a voltage between the first member to be joined and the second member to be joined to join the first member to be joined and the second member to be joined together.

A semiconductor structure bonding apparatus is disclosed. The apparatus may include a leveling adjustment system configured to provide leveling adjustment of upper and lower block assemblies of the apparatus. In some cases, the leveling adjustment system may include a plurality of threaded posts, differentially threaded adjustment collars, and leveling sleeves. In some instances, the leveling adjustment system further may include a plurality of preload springs configured to provide a given preload capacity and range of adjustment. In some instances, the leveling adjustment system further may include a load cell through which one of the threaded posts may be inserted. In some embodiments, the upper block assembly further may include a reaction plate configured to reduce deformation of the upper block assembly. In some embodiments, the upper block assembly further may include a thermal isolation plate configured to provide compliance deflection and being of monolithic or polylithic construction, as desired.

Methods for the production of a semiconductor device are disclosed. In one embodiment, a method may include: (1) mechanically contacting a first substrate (100) having a semiconductor material to a second substrate (200) having a bondable passivation material and contact vias (210) extending through the bondable passivation material; (2) covering the contact vias (210) with an at least high-resistance material (220, 300) on a side facing away from the first substrate (100); (3) applying an electric potential between the at least high-resistance material and the first substrate. The potential has a sufficient level that is functionally sufficient to initiate a bonding process between the bondable passivation material of the second substrate and the semiconductor material of the first substrate.

A parameter adjustment method includes an acquisition process and a parameter changing process. The acquisition process acquires, from an inspection apparatus configured to inspect a combined substrate in which the first substrate and the second substrate are bonded by the bonding apparatus, an inspection result indicating a direction and a degree of distortion occurring in the combined substrate. The parameter changing process changes at least one of multiple parameters including at least one of the gap, an attraction pressure of the first substrate by the first holder, an attraction pressure of the second substrate by the second holder or a pressing force on the first substrate by the striker, based on trend information indicating a tendency of a change in the direction and the degree of the distortion when each of the multiple parameters is changed and the inspection result acquired in the acquiring of the inspection result.

Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.

A method for forming semiconductor devices includes: attaching a glass structure to a wide band-gap semiconductor wafer having a plurality of semiconductor devices; forming at least one pad structure electrically connected to at least one doping region of a semiconductor substrate of the wide band-gap semiconductor wafer, by forming electrically conductive material within at least one opening extending through the glass structure; and reducing a thickness of the wide band-gap semiconductor wafer after attaching the glass structure. Additional methods for forming semiconductor devices are described.

An integrated circuit includes a first chip bonded to a second chip. The first chip includes gate all around transistors on a substrate. The first chip includes backside conductive vias extending through the substrate to the gate all around transistors. The second chip includes electronic circuitry electrically connected to the transistors by the backside conductive vias.

An integrated circuit includes a first chip bonded to a second chip. The first chip includes gate all around transistors on a substrate. The first chip includes backside conductive vias extending through the substrate to the gate all around transistors. The second chip includes electronic circuitry electrically connected to the transistors by the backside conductive vias.

A method for forming semiconductor devices includes attaching a glass structure to a wide band-gap semiconductor wafer having a plurality of semiconductor devices. The method further includes forming at least one pad structure electrically connected to at least one doping region of a semiconductor substrate of the wide band-gap semiconductor wafer, by forming electrically conductive material within at least one opening extending through the glass structure.