H01L2224/84862

Packaged Electronic Device With Film Isolated Power Stack
20210265246 · 2021-08-26 ·

A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

Packaged electronic device with film isolated power stack

A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

Packaged electronic device with film isolated power stack

A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

PACKAGED ELECTRONIC DEVICE WITH FILM ISOLATED POWER STACK

A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

PACKAGED ELECTRONIC DEVICE WITH FILM ISOLATED POWER STACK

A packaged electronic device includes a stacked configuration of a first semiconductor die in a first recess in a first side of a first conductive plate, a second semiconductor die in a second recess in a first side of a second conductive plate, a third conductive plate electrically coupled to a second side of the second semiconductor die, and a package structure that encloses the first semiconductor die, and the second semiconductor die, where the package structure includes a side that exposes a portion of a second side of the first conductive plate.

DIE BONDING MATERIAL, LIGHT-EMITTING DEVICE, AND METHOD FOR PRODUCING LIGHT-EMITTING DEVICE

The present invention provides a die bonding material containing the following component (A) and a solvent and having a refractive index (nD) at 25 C. of 1.41 to 1.43 and a thixotropic index of 2 or more, a light-emitting device including an adhesive member derived from the die bonding material, and a method for producing the light-emitting device. The die bonding material of the present invention is preferably used for fixing a light emitting element at a predetermined position.

Component (A): a curable polysilsesquioxane compound having a repeating unit represented by the following formula (a-1) and satisfying predetermined requirements related to .sup.29Si-NMR and mass average molecular weight (Mw)


R.sup.1-D-SiO.sub.3/2 (a-1)

[wherein R.sup.1 represents a fluoroalkyl group represented by a compositional formula: C.sub.mH.sub.(2m-n+1)F.sub.n; m represents an integer of 1 to 10, and n represents an integer of 2 to (2m+1); and D represents a linking group (excluding an alkylene group) for connecting R.sup.1 and Si, or a single bond].

Multi-Clip Structure for Die Bonding
20200105707 · 2020-04-02 ·

A multi-clip structure includes a first clip for die bonding and a second clip for die bonding. The multi-clip structure further includes a retaining tape fixed to the first clip and to the second clip to hold the first clip and the second clip together.

Multi-Clip Structure for Die Bonding
20200105707 · 2020-04-02 ·

A multi-clip structure includes a first clip for die bonding and a second clip for die bonding. The multi-clip structure further includes a retaining tape fixed to the first clip and to the second clip to hold the first clip and the second clip together.

Semiconductor device

The semiconductor device of the present invention is a semiconductor device in which a first semiconductor chip including a first field effect transistor for a high-side switch, a second semiconductor chip including a second field effect transistor for a low-side switch, and a third semiconductor chip including a circuit that controls each of the first and second semiconductor chips are sealed with a sealing portion. A lead electrically connected to a pad of the first semiconductor chip for a source of the first field effect transistor and a lead electrically connected to a back-surface electrode of the second semiconductor chip for a drain of the second field effect transistor are disposed on the same side of the sealing portion in a plan view.

Semiconductor device

The semiconductor device of the present invention is a semiconductor device in which a first semiconductor chip including a first field effect transistor for a high-side switch, a second semiconductor chip including a second field effect transistor for a low-side switch, and a third semiconductor chip including a circuit that controls each of the first and second semiconductor chips are sealed with a sealing portion. A lead electrically connected to a pad of the first semiconductor chip for a source of the first field effect transistor and a lead electrically connected to a back-surface electrode of the second semiconductor chip for a drain of the second field effect transistor are disposed on the same side of the sealing portion in a plan view.