A semiconductor package includes: a substrate including an insulating layer, a plurality of pads on the insulating layer, a surface protective layer covering the insulating layer and having first through-holes exposing at least a portion of the insulating layer and second through-holes exposing at least a portion of each of the plurality of pads, a plurality of first dummy patterns extending from the plurality of pads to the first through-holes, and a plurality of second dummy patterns extending from the first through-holes to an edge of the insulating layer; a semiconductor chip on the substrate and including connection terminals electrically connected to the plurality of pads exposed through the second through-holes; and an encapsulant encapsulating at least a portion of the semiconductor chip and filling the first through-holes, wherein a separation distance between the first through-holes is greater than a separation distance between the second through-holes.

A semiconductor package including a redistribution substrate with a first insulating layer, one or more second insulating layers on the first insulating layer, and a plurality of redistribution layers. The first insulating layer includes a first photosensitive resin having an elongation of 60% or more and toughness of 70 mJ/mm.sup.3 or more. The one or more second insulating layers include a second photosensitive resin having an elongation in a range of 10% to 40% and toughness of 40 mJ/mm.sup.3.

A semiconductor package including a redistribution substrate with a first insulating layer, one or more second insulating layers on the first insulating layer, and a plurality of redistribution layers. The first insulating layer includes a first photosensitive resin having an elongation of 60% or more and toughness of 70 mJ/mm.sup.3 or more. The one or more second insulating layers include a second photosensitive resin having an elongation in a range of 10% to 40% and toughness of 40 mJ/mm.sup.3.

A packaged integrated circuit device includes a substrate having a surface thereon. A spacer and a first semiconductor chip are provided at spaced-apart locations on a first portion of the surface of the substrate. This first portion of the surface of the substrate has a lateral area equivalent to a sum of: (i) a lateral footprint of the spacer, (ii) a lateral footprint of the first semiconductor chip, and (iii) an area of an entire lateral space between the spacer and the first semiconductor chip. A stack of second semiconductor chips is provided, which extends on the spacer and on the first semiconductor chip. The stack of second semiconductor chips has a lateral footprint greater than the lateral area of the first portion of the surface of the substrate so that at least a portion of the stack of second semiconductor chips overhangs at least one sidewall of at least one of the spacer and the first semiconductor chip, which extend between the stack of second semiconductor chips and the surface of the substrate.

A packaged integrated circuit device includes a substrate having a surface thereon. A spacer and a first semiconductor chip are provided at spaced-apart locations on a first portion of the surface of the substrate. This first portion of the surface of the substrate has a lateral area equivalent to a sum of: (i) a lateral footprint of the spacer, (ii) a lateral footprint of the first semiconductor chip, and (iii) an area of an entire lateral space between the spacer and the first semiconductor chip. A stack of second semiconductor chips is provided, which extends on the spacer and on the first semiconductor chip. The stack of second semiconductor chips has a lateral footprint greater than the lateral area of the first portion of the surface of the substrate so that at least a portion of the stack of second semiconductor chips overhangs at least one sidewall of at least one of the spacer and the first semiconductor chip, which extend between the stack of second semiconductor chips and the surface of the substrate.

A package structure is provided. The package structure includes a die, a lead frame, and a conductive glue. The lead frame includes a die pad and a retaining wall structure. The die pad is configured to support the die, and the retaining wall structure surrounds the die. The conductive glue is disposed between the die and the lead frame.

A package structure is provided. The package structure includes a die, a lead frame, and a conductive glue. The lead frame includes a die pad and a retaining wall structure. The die pad is configured to support the die, and the retaining wall structure surrounds the die. The conductive glue is disposed between the die and the lead frame.

A semiconductor package includes a redistribution structure including an insulating layer having an upper surface and a lower surface, a redistribution pad and a redistribution pattern on the lower surface of the insulating layer and electrically connected to each other, and a passivation layer on the lower surface of the insulating layer and having an opening exposing at least a portion of the redistribution pad; a semiconductor chip on the redistribution structure and including a connection pad electrically connected to the redistribution pad; an encapsulant on the redistribution structure and encapsulating the semiconductor chip; and a connection bump and a dummy bump on the passivation layer, wherein the redistribution pattern has a width narrower than a width of the redistribution pad, the connection bump vertically overlaps the redistribution pad, and the dummy bump vertically overlaps the redistribution pattern.

A semiconductor package includes a redistribution structure including an insulating layer having an upper surface and a lower surface, a redistribution pad and a redistribution pattern on the lower surface of the insulating layer and electrically connected to each other, and a passivation layer on the lower surface of the insulating layer and having an opening exposing at least a portion of the redistribution pad; a semiconductor chip on the redistribution structure and including a connection pad electrically connected to the redistribution pad; an encapsulant on the redistribution structure and encapsulating the semiconductor chip; and a connection bump and a dummy bump on the passivation layer, wherein the redistribution pattern has a width narrower than a width of the redistribution pad, the connection bump vertically overlaps the redistribution pad, and the dummy bump vertically overlaps the redistribution pattern.

A cathode configured for a solid-state battery includes a body having grains of inorganic material sintered to one another, wherein the grains comprise lithium. A thickness of the body is from 3 μm to 100 μm. The first major surface and the second major surface have an unpolished granular profile such that the profile includes grains protruding outward from the respective major surface with a height of at least 25 nm and no more than 150 μm relative to recessed portions of the respective major surface at boundaries between the respective grains.