An SIP module includes a plurality of electrical components mounted to an interconnect substrate. The electrical components and interconnect substrate are covered by an encapsulant. A conductive post is formed through the encapsulant. A plurality of openings is formed in the encapsulant by laser in a form of a circuit pattern. A conductive material is deposited over a surface of the encapsulant and into the openings to form an electrical circuit pattern. A portion of the conductive material is removed by a grinder to expose the electrical circuit pattern. The grinding operation planarizes the surface of the encapsulant and the electrical circuit pattern. The electrical circuit pattern can be a trace, contact pad, RDL, or other interconnect structure. The electrical circuit pattern can also be a shielding layer or antenna. An electrical component is disposed over the SIP module and electrical circuit pattern.

An SIP module includes a plurality of electrical components mounted to an interconnect substrate. The electrical components and interconnect substrate are covered by an encapsulant. A conductive post is formed through the encapsulant. A plurality of openings is formed in the encapsulant by laser in a form of a circuit pattern. A conductive material is deposited over a surface of the encapsulant and into the openings to form an electrical circuit pattern. A portion of the conductive material is removed by a grinder to expose the electrical circuit pattern. The grinding operation planarizes the surface of the encapsulant and the electrical circuit pattern. The electrical circuit pattern can be a trace, contact pad, RDL, or other interconnect structure. The electrical circuit pattern can also be a shielding layer or antenna. An electrical component is disposed over the SIP module and electrical circuit pattern.

An SIP module includes a plurality of electrical components mounted to an interconnect substrate. The electrical components and interconnect substrate are covered by an encapsulant. A conductive post is formed through the encapsulant. A plurality of openings is formed in the encapsulant by laser in a form of a circuit pattern. A conductive material is deposited over a surface of the encapsulant and into the openings to form an electrical circuit pattern. A portion of the conductive material is removed by a grinder to expose the electrical circuit pattern. The grinding operation planarizes the surface of the encapsulant and the electrical circuit pattern. The electrical circuit pattern can be a trace, contact pad, RDL, or other interconnect structure. The electrical circuit pattern can also be a shielding layer or antenna. An electrical component is disposed over the SIP module and electrical circuit pattern.

An SIP module includes a plurality of electrical components mounted to an interconnect substrate. The electrical components and interconnect substrate are covered by an encapsulant. A conductive post is formed through the encapsulant. A plurality of openings is formed in the encapsulant by laser in a form of a circuit pattern. A conductive material is deposited over a surface of the encapsulant and into the openings to form an electrical circuit pattern. A portion of the conductive material is removed by a grinder to expose the electrical circuit pattern. The grinding operation planarizes the surface of the encapsulant and the electrical circuit pattern. The electrical circuit pattern can be a trace, contact pad, RDL, or other interconnect structure. The electrical circuit pattern can also be a shielding layer or antenna. An electrical component is disposed over the SIP module and electrical circuit pattern.

A semiconductor package includes a package substrate; a plurality of lower chip structures on the package substrate; an upper chip structure on the plurality of lower chip structures and covering portions of upper surfaces of the plurality of lower chip structures; a non-conductive adhesive layer on a lower surface of the upper chip structure and receiving upper portions of the plurality of lower chip structures; and a molded member on the plurality of lower chip structures and the upper chip structure.

A semiconductor package includes a package substrate; a plurality of lower chip structures on the package substrate; an upper chip structure on the plurality of lower chip structures and covering portions of upper surfaces of the plurality of lower chip structures; a non-conductive adhesive layer on a lower surface of the upper chip structure and receiving upper portions of the plurality of lower chip structures; and a molded member on the plurality of lower chip structures and the upper chip structure.

Provided is copper paste for joining including metal particles, and a dispersion medium. The metal particles include sub-micro copper particles having a volume-average particle size of 0.12 m to 0.8 m, and micro copper particles having a volume-average particle size of 2 m to 50 m, a sum of the amount of the sub-micro copper particles contained and the amount of the micro copper particles contained is 80% by mass or greater on the basis of a total mass of the metal particles, and the amount of the sub-micro copper particles contained is 30% by mass to 90% by mass on the basis of a sum of a mass of the sub-micro copper particles and a mass of the micro copper particles.

Provided is copper paste for joining including metal particles, and a dispersion medium. The metal particles include sub-micro copper particles having a volume-average particle size of 0.12 m to 0.8 m, and micro copper particles having a volume-average particle size of 2 m to 50 m, a sum of the amount of the sub-micro copper particles contained and the amount of the micro copper particles contained is 80% by mass or greater on the basis of a total mass of the metal particles, and the amount of the sub-micro copper particles contained is 30% by mass to 90% by mass on the basis of a sum of a mass of the sub-micro copper particles and a mass of the micro copper particles.

Provided is copper paste for joining including metal particles, and a dispersion medium. The metal particles include sub-micro copper particles having a volume-average particle size of 0.12 m to 0.8 m, and micro copper particles having a volume-average particle size of 2 m to 50 m, a sum of the amount of the sub-micro copper particles contained and the amount of the micro copper particles contained is 80% by mass or greater on the basis of a total mass of the metal particles, and the amount of the sub-micro copper particles contained is 30% by mass to 90% by mass on the basis of a sum of a mass of the sub-micro copper particles and a mass of the micro copper particles.

Provided is copper paste for joining including metal particles, and a dispersion medium. The metal particles include sub-micro copper particles having a volume-average particle size of 0.12 m to 0.8 m, and micro copper particles having a volume-average particle size of 2 m to 50 m, a sum of the amount of the sub-micro copper particles contained and the amount of the micro copper particles contained is 80% by mass or greater on the basis of a total mass of the metal particles, and the amount of the sub-micro copper particles contained is 30% by mass to 90% by mass on the basis of a sum of a mass of the sub-micro copper particles and a mass of the micro copper particles.