Semiconductor device includes: semiconductor elements electrically connected in parallel; pad portion electrically connected to the semiconductor elements; and terminal portion electrically connected to the pad portion. As viewed in thickness direction, the semiconductor elements are aligned along first direction perpendicular to the thickness direction. The pad portion includes closed region surrounded by three line segments each formed by connecting two of first, second and third vertex not disposed on the same straight line. As viewed in thickness direction, the first vertex overlaps with one semiconductor element located in outermost position in first sense of the first direction. As viewed in the thickness direction, the second vertex overlaps with one semiconductor element located in outermost position in second sense of the first direction. As viewed in the thickness direction, the third vertex is located on perpendicular bisector of the line segment connecting the first and second vertex.

A semiconductor device includes: a semiconductor chip; a case having a frame portion that has an inner wall portion surrounding an housing area in which the semiconductor chip is disposed; a buffer member provided on at last part of the inner wall portion of the case on a side of the housing area; a low expansion member provided on said at least part of the inner wall portion with the buffer member interposed therebetween on the side of the housing area; and a sealing member that seals the housing area, wherein the buffer member has a smaller elastic modulus than the case and the sealing member, and wherein the low expansion member has a smaller linear expansion coefficient than the case and the sealing member.

A semiconductor device includes: a semiconductor chip; a case having a frame portion that has an inner wall portion surrounding an housing area in which the semiconductor chip is disposed; a buffer member provided on at last part of the inner wall portion of the case on a side of the housing area; a low expansion member provided on said at least part of the inner wall portion with the buffer member interposed therebetween on the side of the housing area; and a sealing member that seals the housing area, wherein the buffer member has a smaller elastic modulus than the case and the sealing member, and wherein the low expansion member has a smaller linear expansion coefficient than the case and the sealing member.

A stacked integrated circuit (IC) system including a substrate, a contour support, and a first and second IC dies. The contour support including a first support frame attached to the substrate defining a first lateral contact surface substantially orthogonal to the substrate, a support plate on the first support frame substantially parallel to the substrate, and a second support frame on the support plate defining a second lateral contact surface substantially orthogonal to the substrate, with the first and second lateral contact surfaces laterally offset from each other. The first integrated circuit die with a side abutting the first lateral contact surface, the second integrated circuit die with a side abutting the second lateral contact surface such that at least a portion of the support plate is between the first and second integrated circuit dies.

A semiconductor device includes: a semiconductor chip; a case having a frame portion that has an inner wall portion surrounding an housing area in which the semiconductor chip is disposed; a buffer member provided on at last part of the inner wall portion of the case on a side of the housing area; a low expansion member provided on said at least part of the inner wall portion with the buffer member interposed therebetween on the side of the housing area; and a sealing member that seals the housing area, wherein the buffer member has a smaller elastic modulus than the case and the sealing member, and wherein the low expansion member has a smaller linear expansion coefficient than the case and the sealing member.

A semiconductor device includes: a semiconductor chip; a case having a frame portion that has an inner wall portion surrounding an housing area in which the semiconductor chip is disposed; a buffer member provided on at last part of the inner wall portion of the case on a side of the housing area; a low expansion member provided on said at least part of the inner wall portion with the buffer member interposed therebetween on the side of the housing area; and a sealing member that seals the housing area, wherein the buffer member has a smaller elastic modulus than the case and the sealing member, and wherein the low expansion member has a smaller linear expansion coefficient than the case and the sealing member.

A package comprising a base is provided. An electrode and a concave portion are arranged on a first surface of the package. The base comprises a second surface on a side opposite to the first surface and a third surface. The first surface is positioned between the second and third surfaces. The electrode comprises an electrode upper surface and an electrode side surface. The concave portion comprises a concave side surface and a bottom surface positioned closer to the second surface than the concave side surface. The electrode upper surface is arranged at a position further away from the virtual plane than the bottom surface. The electrode side surface is continuous with the concave side surface. The concave portion further comprises a second side surface which faces the concave side surface and is continuous with the third surface.

A package comprising a base is provided. An electrode and a concave portion are arranged on a first surface of the package. The base comprises a second surface on a side opposite to the first surface and a third surface. The first surface is positioned between the second and third surfaces. The electrode comprises an electrode upper surface and an electrode side surface. The concave portion comprises a concave side surface and a bottom surface positioned closer to the second surface than the concave side surface. The electrode upper surface is arranged at a position further away from the virtual plane than the bottom surface. The electrode side surface is continuous with the concave side surface. The concave portion further comprises a second side surface which faces the concave side surface and is continuous with the third surface.

A package comprising a base is provided. An electrode and a concave portion are arranged on a first surface of the package. The base comprises a second surface on a side opposite to the first surface and a third surface. The first surface is positioned between the second and third surfaces. The electrode comprises an electrode upper surface and an electrode side surface. The concave portion comprises a concave side surface and a bottom surface positioned closer to the second surface than the concave side surface. The electrode upper surface is arranged at a position further away from the virtual plane than the bottom surface. The electrode side surface is continuous with the concave side surface. The concave portion further comprises a second side surface which faces the concave side surface and is continuous with the third surface.

A package comprising a base is provided. An electrode and a concave portion are arranged on a first surface of the package. The base comprises a second surface on a side opposite to the first surface and a third surface. The first surface is positioned between the second and third surfaces. The electrode comprises an electrode upper surface and an electrode side surface. The concave portion comprises a concave side surface and a bottom surface positioned closer to the second surface than the concave side surface. The electrode upper surface is arranged at a position further away from the virtual plane than the bottom surface. The electrode side surface is continuous with the concave side surface. The concave portion further comprises a second side surface which faces the concave side surface and is continuous with the third surface.