Patent classifications
H01L2224/85897
Semiconductor device manufacturing method and soldering support jig
A semiconductor device manufacturing method includes: applying solder to an arrangement area of a substrate, the substrate having a connection area to which a wiring member is to be directly connected, the connection area neighboring the arrangement area; arranging a component on the arrangement area via the solder; and soldering the component to the arrangement area by heating the solder while covering the connection area. A soldering support jig includes a columnar covering member having a covering surface at a bottom of the columnar covering member.
Bonding wire having a silver alloy core, wire bonding method using the bonding wire, and electrical connection part of semiconductor device using the bonding wire
A bonding wire includes a wire core including a silver-palladium alloy. A coating layer is disposed on a sidewall of the wire core. A palladium content of the silver-palladium alloy ranges from about 0.1 wt % to about 1.5 wt %.
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SOLDERING SUPPORT JIG
A semiconductor device manufacturing method includes: applying solder to an arrangement area of a substrate, the substrate having a connection area to which a wiring member is to be directly connected, the connection area neighboring the arrangement area; arranging a component on the arrangement area via the solder; and soldering the component to the arrangement area by heating the solder while covering the connection area. A soldering support jig includes a columnar covering member having a covering surface at a bottom of the columnar covering member.
Semiconductor device manufacturing method and soldering support jig
A semiconductor device manufacturing method includes: applying solder to an arrangement area of a substrate, the substrate having a connection area to which a wiring member is to be directly connected, the connection area neighboring the arrangement area; arranging a component on the arrangement area via the solder; and soldering the component to the arrangement area by heating the solder while covering the connection area. A soldering support jig includes a columnar covering member having a covering surface at a bottom of the columnar covering member.
SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SOLDERING SUPPORT JIG
A semiconductor device manufacturing method includes: applying solder to an arrangement area of a substrate, the substrate having a connection area to which a wiring member is to be directly connected, the connection area neighboring the arrangement area; arranging a component on the arrangement area via the solder; and soldering the component to the arrangement area by heating the solder while covering the connection area. A soldering support jig includes a columnar covering member having a covering surface at a bottom of the columnar covering member.
BONDING WIRE, WIRE BONDING METHOD USING THE BONDING WIRE, AND ELECTRICAL CONNECTION PART OF SEMICONDUCTOR DEVICE USING THE BONDING WIRE
A bonding wire includes a wire core including a silver-palladium alloy, and a coating layer disposed on a sidewall of the wire core. A palladium content of the silver-palladium alloy ranges from about 0.1 wt % to about 1.5 wt %.
ELECTRONIC DEVICE INCLUDING STACKED SEMICONDUCTOR CHIPS AND METHOD OF MANUFACTURING THE SAME
An electronic device and a manufacturing method are provided. The electronic device includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and is electrically connected to the first semiconductor chip by hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip, and is electrically connected to the second semiconductor chip through a plurality of bumps.
ELECTRONIC DEVICE INCLUDING STACKED SEMICONDUCTOR CHIPS AND METHOD OF MANUFACTURING THE SAME
An electronic device and a manufacturing method are provided. The electronic device includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and is electrically connected to the first semiconductor chip by hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip, and is electrically connected to the second semiconductor chip through a plurality of bumps.
DIRECT COPPER WIRE BONDING ON NANOTWIN COPPER STRUCTURES
A package comprises a semiconductor die including a device side having circuitry formed therein. The package includes a metal member coupled to the device side and a nanotwin copper member having a bottom surface coupled to the metal member, the nanotwin copper member comprising a twin boundary separating a first region having a first grain structure from a second region having a second grain structure. The package also comprises a wire bond coupled directly to a top surface of the nanotwin copper member, the wire bond contacting multiple regions of the nanotwin copper member. The package also comprises a mold compound covering the die, the metal member, the nanotwin copper member, and the wire bond.