Patent classifications
H01L2224/95121
Wet alignment method for micro-semiconductor chip and display transfer structure
A wet alignment method for a micro-semiconductor chip and a display transfer structure are provided. The wet alignment method for a micro-semiconductor chip includes: supplying a liquid to a transfer substrate including a plurality of grooves; supplying the micro-semiconductor chip onto the transfer substrate; scanning the transfer substrate by using an absorber capable of absorbing the liquid. According to the wet alignment method, the micro-semiconductor chip may be transferred onto a large area.
Wet alignment method for micro-semiconductor chip and display transfer structure
A wet alignment method for a micro-semiconductor chip and a display transfer structure are provided. The wet alignment method for a micro-semiconductor chip includes: supplying a liquid to a transfer substrate including a plurality of grooves; supplying the micro-semiconductor chip onto the transfer substrate; scanning the transfer substrate by using an absorber capable of absorbing the liquid. According to the wet alignment method, the micro-semiconductor chip may be transferred onto a large area.
NANOSCALE-ALIGNED THREE-DIMENSIONAL STACKED INTEGRATED CIRCUIT
A method for fabricating a three-dimensional (3D) stacked integrated circuit. Pick-and-place strategies are used to stack the source wafers with device layers fabricated using standard two-dimensional (2D) semiconductor fabrication technologies. The source wafers may be stacked in either a sequential or parallel fashion. The stacking may be in a face-to-face, face-to-back, back-to-face or back-to-back fashion. The source wafers that are stacked in a face-to-back, back-to-face or back-to-back fashion may be connected using Through Silicon Vias (TSVs). Alternatively, source wafers that are stacked in a face-to-face fashion may be connected using Inter Layer Vias (ILVs).
Shift control method in manufacture of semiconductor device
A shift control method in manufacture of semiconductor device includes at least the following step. An overlay offset of a first target of a semiconductor die and a second target of the semiconductor die is determined, where the second target is disposed on the first target. The semiconductor die is placed over a carrier, where placing the semiconductor die includes feeding back the overlay offset to result in a positional control of the semiconductor die. The semiconductor die is post processed to form a semiconductor device. Other shift control methods in manufacture of semiconductor device are also provided.
WET ALIGNMENT METHOD FOR MICRO-SEMICONDUCTOR CHIP AND DISPLAY TRANSFER STRUCTURE
A wet alignment method for a micro-semiconductor chip and a display transfer structure are provided. The wet alignment method for a micro-semiconductor chip includes: supplying a liquid to a transfer substrate including a plurality of grooves; supplying the micro-semiconductor chip onto the transfer substrate; scanning the transfer substrate by using an absorber capable of absorbing the liquid. According to the wet alignment method, the micro-semiconductor chip may be transferred onto a large area.
WET ALIGNMENT METHOD FOR MICRO-SEMICONDUCTOR CHIP AND DISPLAY TRANSFER STRUCTURE
A wet alignment method for a micro-semiconductor chip and a display transfer structure are provided. The wet alignment method for a micro-semiconductor chip includes: supplying a liquid to a transfer substrate including a plurality of grooves; supplying the micro-semiconductor chip onto the transfer substrate; scanning the transfer substrate by using an absorber capable of absorbing the liquid. According to the wet alignment method, the micro-semiconductor chip may be transferred onto a large area.
High speed handling of ultra-small chips by selective laser bonding and debonding
Techniques for high speed handling of ultra-small chips (e.g., micro-chips) by selective laser bonding and/or debonding are provided. In one aspect, a method includes: providing a first wafer including chips bonded to a surface thereof; contacting the first wafer with a second wafer, the second wafer including a substrate bonded to a surface thereof, wherein the contacting aligns individual chips with bonding sites on the substrate; and debonding the individual chips from the first wafer using a debonding laser having a small spot size of about 0.5 μm to about 100 μm, and ranges therebetween. A system is also provided that has digital cameras, a motorized XYZ-axis stage, and a computer control system configured to i) control a spot size of the at least one laser source and ii) adjust a positioning of the sample to align individual chips with a target area of the laser.
WET ALIGNMENT METHOD FOR MICRO-SEMICONDUCTOR CHIP AND DISPLAY TRANSFER STRUCTURE
A wet alignment method for a micro-semiconductor chip and a display transfer structure are provided. The wet alignment method for a micro-semiconductor chip includes: supplying a liquid to a transfer substrate including a plurality of grooves; supplying the micro-semiconductor chip onto the transfer substrate; scanning the transfer substrate by using an absorber capable of absorbing the liquid. According to the wet alignment method, the micro-semiconductor chip may be transferred onto a large area.
WET ALIGNMENT METHOD FOR MICRO-SEMICONDUCTOR CHIP AND DISPLAY TRANSFER STRUCTURE
A wet alignment method for a micro-semiconductor chip and a display transfer structure are provided. The wet alignment method for a micro-semiconductor chip includes: supplying a liquid to a transfer substrate including a plurality of grooves; supplying the micro-semiconductor chip onto the transfer substrate; scanning the transfer substrate by using an absorber capable of absorbing the liquid. According to the wet alignment method, the micro-semiconductor chip may be transferred onto a large area.
SHIFT CONTROL METHOD IN MANUFACTURE OF SEMICONDUCTOR DEVICE
A shift control method in manufacture of semiconductor device includes at least the following step. A plurality of semiconductor dies is encapsulated with an insulating encapsulation over a carrier, where at least portions of the plurality of semiconductor dies are shifted after encapsulating. A lithographic pattern is formed at least on the plurality of semiconductor die, where forming the lithographic pattern includes compensating for a shift in a position of the portions of the plurality of semiconductor dies.