An interposer comprises a semiconductor material and includes cache memory under a location on the interposer for a host device. Memory interface circuitry may also be located under one or more locations on the interposer for memory devices. Microelectronic device assemblies incorporating such an interposer and comprising a host device and multiple memory devices are also disclosed, as are methods of fabricating such microelectronic device assemblies.

A semiconductor package structure is provided. The semiconductor package structure includes a carrier, a first electronic component, a second electronic component, a third electronic component, a fourth electronic component, and a connection element. The first electronic component is disposed over a surface of the carrier. The second electronic component is disposed over the first electronic component. The third electronic component is spaced apart from the first electronic component and disposed over the surface of the carrier. The fourth electronic component is disposed over the third electronic component. The connection element is electrically connecting the second electronic component to the fourth electronic component.

Embodiments described herein may be related to apparatuses, processes, and techniques related to multilevel dies, in particular to photonics integrated circuit dies with a thick portion and a thin portion, where the thick portion is placed within a cavity in a substrate and the thin portion serves as an overhang to physically couple with the substrate, to reduce a distance between electrical contacts on the thin portion of the die and electrical contacts on the substrate. Other embodiments may be described and/or claimed.

An electronic substrate may be fabricated having a core comprising a laminate including a metal layer between a first insulator layer and a second insulator layer, a metal via through the core, and metallization features on a first side and a second side of the core, wherein first ones of the metallization features are embedded within dielectric material on the first side of the core, and wherein a sidewall of the dielectric material and of the first insulator layer defines a recess over an area of the metal layer. In an embodiment of the present description, an integrated circuit package may be formed with the electronic substrate, wherein at least two integrated circuit devices may be attached to the electronic substrate. In a further embodiment, the integrated circuit package may be electrically attached to an electronic board. Other embodiments are disclosed and claimed.

A semiconductor device includes a substrate. The semiconductor device further includes a waveguide on a first side of the substrate. The semiconductor device further includes a photodetector (PD) on a second side of the substrate, opposite the first side of the substrate. The semiconductor device further includes an optical through via (OTV) optically connecting the PD with the waveguide, wherein the OTV extends through the substrate from the first side of the substrate to the second side of the substrate.

A semiconductor package includes a base substrate structure having a top surface that includes conductive regions disposed in a dielectric region. The conductive regions are coupled to an interconnect structure. The semiconductor package also includes a first die bonded sideways on the base substrate structure. A side surface at an edge of the first die is bonded to the top surface of the base substrate structure. A front surface of the first die is perpendicular to the top surface of the base substrate structure. The first die includes a photonic device on a substrate of the first die, and the substrate includes an optical interface for coupling a back surface of the first die to an optical fiber.

Embodiments utilize a bridge die that directly bonds to and bridges two or more device dies. Each of the device dies can have additional device dies stacked thereupon. In some embodiments, the bridge die can bridge device dies disposed both under and over the bridge die. In some embodiments, several bridge dies may be used to bridge a device die to other adjacent device dies.

A semiconductor package including a first die, a second die and a transparent encapsulation material is provided. The first die includes a first substrate and an optical coupler formed on the first substrate. The second die is disposed on the first die and includes a transparent portion overlapping the optical coupler. The transparent encapsulation material is disposed on the first die and laterally encapsulates the second die.

An optical interconnection system and method are provided. The system includes two or more basic components that are stacked and interconnected. The basic component includes an optical network layer and an electrical layer, where in each basic component, the optical network layer is electrically interconnected with the electrical layer, and the optical network layer of each basic component is optically interconnected with an optical network layer of an adjacent basic component, and through optical interconnection in three-dimensional space, a limitation on a quantity of stacked electrical layers is reduced, and efficiency of signal transmission is increased.

According to one general aspect, an apparatus may include a memory circuit die configured to store a lookup table that converts first data to second data. The apparatus may also include a logic circuit die comprising combinatorial logic circuits configured to receive the second data. The apparatus may further include an optical via coupled between the memory circuit die and the logical circuit die and configured to transfer second data between the memory circuit die and the logic circuit die.