A semiconductor package includes a semiconductor die and an encapsulant layer. A mark is formed on a surface of the encapsulant layer. A damage barrier layer is disposed between the mark and the semiconductor die. The damage barrier layer blocks the propagation of laser light used to form the mark from reaching the semiconductor die.

A memory device includes a memory array, a circuit structure, a bonding structure between the memory array and the circuit structure, and a shielding structure between the memory array and the circuit structure and surrounding the bonding structure. The bonding structure includes a first bonding pattern and a second bonding pattern. The circuit structure is electrically connected with the memory array through the bonding structure. The shielding structure includes a third bonding pattern and a fourth bonding pattern. The first bonding pattern is in contact with the second bonding pattern at a first interface between the first bonding pattern and the second bonding pattern. The third bonding pattern is in contact with the fourth bonding pattern at a second interface between the third bonding pattern and the fourth bonding pattern.

Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate and the components are connected with conductive material in preformed holes in dielectric material in the bond lines aligned with TSVs of the devices and the exposed conductors of the substrate. Methods of fabrication are also disclosed.

According to one embodiment, a magnetic memory device includes a magnetic memory chip having a magnetoresistive element, a magnetic layer having first and second portions spacing out each other, the first portion covering a first main surface of the magnetic memory chip, the second portion covering a second main surface facing the first main surface of the magnetic memory chip, a circuit board on which the magnetic layer is mounted, and a bonding wire connecting between the magnetic memory chip and the circuit board in a first direction parallel to the first and second main surfaces.

A semiconductor device includes: a substrate on which wiring is formed; a first semiconductor element flip-chip bonded to the substrate; a second semiconductor element provided on the first semiconductor element; a first resin provided in at least part of a region between the first semiconductor element and the substrate; a second resin provided in at least part of a region between the second semiconductor element and the substrate; and a member having a thermal conductivity higher than a thermal conductivity of the first resin and a thermal conductivity of the second resin, provided between the first resin and the second resin, having a part overlapping with an upper surface of the first semiconductor element, and having another part overlapping with a first wiring part as part of the wiring in a top view.

In a semiconductor device manufacturing method, a stacked substrate is formed. In the stacked substrate, a substrate is stacked repeatedly multiple times. The substrate includes a plurality of chip regions. In the semiconductor device manufacturing method, the stacked substrate is cut in a stacking direction among the plurality of chip regions, to separate the stacked substrate into a plurality of stacked bodies. In forming the stacked substrate, a first main surface of a first substrate and a second main surface of a second substrate are bonded to each other. In forming the stacked substrate, in a state where the second main surface is bonded to the first main surface, a third main surface of the second substrate opposite to the second main surface is thinned. In forming the stacked substrate, the third main surface of the second substrate and a fourth main surface of a third substrate are bonded to each other. In forming the stacked substrate, in a state where the fourth main surface is bonded to the third main surface, a fifth main surface of the third substrate opposite to the fourth main surface is thinned.

A tank circuit structure includes a first gate layer, a first substrate, a first shielding layer, a first inductor, a second inductor and a first inter metal dielectric (IMD) layer. The first substrate is over the first gate layer. The first shielding layer is over the first gate layer. The first inductor is over the first shielding layer. The second inductor is below the first substrate. The first IMD layer is between the first substrate and the first shielding layer.

Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components. Further, the shield structure substantially covers the second electronic component and/or would substantially cover the first electronic component if the semiconductor packaging device was flipped vertically.

A semiconductor package is disclosed. The semiconductor package may include a substrate, a first semiconductor chip on the substrate, an inner mold layer provided on the substrate to at least partially enclose the first semiconductor chip, an inner shielding layer provided on the substrate to at least partially enclose the inner mold layer, a second semiconductor chip stack on the inner shielding layer, an outer mold layer provided on the substrate to at least partially enclose the inner shielding layer and the second semiconductor chip stack, and an outer shielding layer at least partially enclosing the outer mold layer. Each of the inner and outer shielding layers may include a conductive material, and the inner shielding layer may be electrically connected to a ground pad of the substrate.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and the second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second semiconductor layer. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer.