In an embodiment, a package includes: a first redistribution structure; a first integrated circuit die connected to the first redistribution structure; a ring-shaped substrate surrounding the first integrated circuit die, the ring-shaped substrate connected to the first redistribution structure, the ring-shaped substrate including a core and conductive vias extending through the core; a encapsulant surrounding the ring-shaped substrate and the first integrated circuit die, the encapsulant extending through the ring-shaped substrate; and a second redistribution structure on the encapsulant, the second redistribution structure connected to the first redistribution structure through the conductive vias of the ring-shaped substrate.

A package structure includes a semiconductor die, conductive pillars, an insulating encapsulation, a redistribution circuit structure, and a solder resist layer. The conductive pillars are arranged aside of the semiconductor die. The insulating encapsulation encapsulates the semiconductor die and the conductive pillars, and the insulating encapsulation has a first surface and a second surface opposite to the first surface. The redistribution circuit structure is located on the first surface of the insulating encapsulation. The solder resist layer is located on the second surface of the insulating encapsulation, wherein a material of the solder resist layer includes a filler.

A fan-out semiconductor package includes a frame substrate having a through hole therein, a semiconductor chip in the through hole, wherein the semiconductor chip includes a chip body, a chip pad on a surface of the chip body and a passivation layer on the chip body and on the chip pad, an encapsulation layer on side surfaces of the semiconductor chip within the through hole, and a guard ring on the passivation layer and on an edge portion of the chip body.

A semiconductor package is disclosed. The semiconductor package may include a first redistribution substrate including a first insulating layer and a first redistribution pattern, a lower semiconductor chip mounted on the first redistribution substrate, a conductive structure disposed on the first redistribution substrate and horizontally spaced apart from the lower semiconductor chip, a first mold layer interposed between the first redistribution substrate and the second redistribution substrate to cover the lower semiconductor chip and the conductive structure, a second redistribution substrate on the first redistribution substrate, the second redistribution substrate including a second insulating layer and a second redistribution pattern, a first heat-dissipation pattern interposed between the lower semiconductor chip and the second insulating layer, and a heat-dissipation pad on the conductive structure. A top surface of the first heat-dissipation pattern may be located at a level higher than a top surface of the conductive structure.

A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure. The first stacked die package structure includes a plurality of memory dies. The underfill layer is over the first stacked die package structure. The underfill layer includes a first protruding portion that extends below a top surface of the through substrate via structure. The package layer is over the underfill layer. The package layer has a second protruding portion that extends below the top surface of the through substrate via structure.

A fan-out semiconductor package includes a frame substrate having a through hole therein, a semiconductor chip in the through hole, wherein the semiconductor chip includes a chip body, a chip pad on a surface of the chip body and a passivation layer on the chip body and on the chip pad, an encapsulation layer on side surfaces of the semiconductor chip within the through hole, and a guard ring on the passivation layer and on an edge portion of the chip body.

A semiconductor device is disclosed. The semiconductor device comprises a redistribution structure, a processor die, and a metal post. The metal post has a first end, and a second end. The metal post is connected to the redistribution structure at the first end. The first end has a first width. The second end has a second width. The metal post has a waist width. The first width is greater than the waist width. The second width is greater than the waist width. The metal post has a side surface. The side surface is inwardly curved or outwardly curved.

The present disclosure relates to a method of manufacturing a semiconductor structure. The method of manufacturing a semiconductor structure includes providing a carrier; disposing a dielectric layer over the carrier; removing a first portion of the dielectric layer to form an opening extending through the dielectric layer; removing a second portion of the dielectric layer to form a trench extending through and along the dielectric layer; disposing a conductive material into the opening and the trench to form a conductive via and a metallic strip, respectively; removing a third portion of the dielectric layer; detaching the dielectric layer from the carrier; disposing the dielectric layer over a substrate; disposing a die over the substrate; and forming a molding to surround the die.

A semiconductor device is disclosed. The semiconductor device comprises a redistribution structure, a processor die, and a metal post. The metal post has a first end, and a second end. The metal post is connected to the redistribution structure at the first end. The first end has a first width. The second end has a second width. The metal post has a waist width. The first width is greater than the waist width. The second width is greater than the waist width. The metal post has a side surface. The side surface is inwardly curved or outwardly curved.

A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure, wherein the first stacked die package structure comprises a plurality of memory dies. The underfill layer is over the first stacked die package structure. the package layer is over the underfill layer, wherein the package layer has a protruding portion that extends below a top surface of the through substrate via structure.