A power semiconductor module includes a substrate with a metallization layer that is structured. A semiconductor chip having a first side bonded to the metallization layer. A metal clip, which is a strip of metal, has a first planar part bonded to a second side of the semiconductor chip opposite to the first side. The metal clip also has a second planar part bonded to the metallization layer. A mold encapsulation at least partially encloses the substrate and the metal clip. The mold encapsulation has a recess approaching towards the first planar part of the metal clip. The semiconductor chip is completely enclosed by the mold encapsulation, the substrate and the metal clip and the first planar part of the metal clip is at least partially exposed by the recess. A sensor is accommodated in the recess.

An object is to provide a technique capable of suppressing generation of a crack in a molding resin and suppressing entry of moisture from the outside. A semiconductor device includes a heat spreader, a semiconductor element provided on an upper surface of the heat spreader, an insulating sheet provided on a lower surface of the heat spreader, a lead frame joined to an upper surface of the semiconductor element via solder, and a molding resin that seals one end side of the lead frame, the semiconductor element, the heat spreader, and the insulating sheet. A hole is formed from an upper surface of the molding resin to a joining surface of the lead frame with the semiconductor element, and the hole is filled with a low Young's modulus resin having a Young's modulus lower than that of the molding resin.

A foil-based package and a method for manufacturing a foil-based package includes, among other things, a first and a second foil substrate. An electronic component is arranged between the two foil substrates in a sandwich-like manner. Due to the component thickness, there is a distance difference between the two foil substrates between the mounting area of the component and ears outside of the mounting area. The foil-based package and the method provides means for reducing and/or compensating a distance difference between the first foil substrate and the second foil substrate caused by the component thickness.

An electronic component package of an embodiment of the disclosure includes a base, a first plated layer, a first electronic component chip, a second plated layer, and a second electronic component chip. The base includes a first surface and a second surface. The first plated layer covers the first surface. The first electronic component chip is provided on the first plated layer with a first insulating layer being interposed therebetween. The second plated layer covers the second surface. The second electronic component chip is provided on the second plated layer with a second insulating layer being interposed therebetween. The first plated layer and the second plated layer each include a first metal material that is less likely to undergo an ion migration phenomenon than silver (Ag).

A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.

A semiconductor device includes: semiconductor elements; a package sealing the semiconductor elements and being rectangular in a top view; control terminals protruding from a first side of the package; output terminals protruding from a second side facing the first side of the package; and a recessed portion formed in a third side adjacent to the first side and the second side of the package, wherein a part of the control terminals is disposed at end portions of lead frames, the semiconductor device further includes dummy terminals disposed at other end portions of the lead frames, respectively, the dummy terminals protruding from the recessed portion, and an amount of the protrusion of each of the dummy terminals from the recessed portion is smaller than or equal to 0.75 mm.

Disclosed are semiconductor packages and methods of manufacturing the same. The method of manufacturing a semiconductor package may include providing a carrier substrate having a trench formed on a first top surface of the carrier substrate, providing a first semiconductor chip on the carrier substrate, mounting at least one second semiconductor chip on a second top surface of the first semiconductor chip, coating a mold member to surround a first lateral surface of the first semiconductor chip and a second lateral surface of the at least one second semiconductor chip, and curing the mold member to form a mold layer. The trench may be provided along a first edge of the first semiconductor chip. The mold member may cover a second edge of a bottom surface the first semiconductor chip.

Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and a mold layer over the package substrate and around the first die. In an embodiment, the electronic package further comprises a through mold opening through the mold layer, and a through mold interconnect (TMI) in the through mold opening, wherein a center of the TMI is offset from a center of the through mold opening.

An electronic component includes a mounting substrate, and first and second devices each including a functional element. The first device is spaced apart from and faces the mounting substrate. The second device is located on the mounting substrate and faces the first device. A functional element of the first device is located on a first surface facing the second device, in the first device. A functional element of the second device is located on a second surface facing the first device, in the second device.

The present disclosure provides a package structure of an air gap type semiconductor device and its fabrication method. The fabrication method includes forming a bonding layer having a first opening on a carrier; disposing a semiconductor chip on the bonding layer, thereby forming a first cavity at the first opening, where the first cavity is at least aligned with a portion of an active region of the semiconductor chip; performing an encapsulation process to encapsulate the semiconductor chip on the carrier; lastly, forming through holes passing through the carrier where each through hole is aligned with a corresponding input/output electrode region of the semiconductor chip, and forming interconnection structures on a side of the carrier different from a side with the bonding layer, where each interconnection structure passes through a corresponding through hole and is electrically connected to an corresponding input/output electrode.