This description relates generally to semiconductor devices and processes. A method for forming a packaged semiconductor package can include attaching a front side of a metal layer to a die pad of a leadframe that includes conductive terminals, so a periphery portion of the metal layer extends beyond a periphery pad surface of the die pad, and a portion of a half-etched cavity on the front side of the metal layer is located near the periphery pad surface of the die pad. The method further includes attaching a semiconductor device to the die pad and encapsulating the semiconductor device, the front side of the metal layer, a portion of a back side of the metal layer, and a portion of the conductive terminals to form a packaged semiconductor device.

A semiconductor device manufacturing method includes a molding step including disposing a control pin between an inlet and a control wire and on a line connecting the inlet and the control wire in a plan view of the semiconductor device, injecting molding resin raw material into a cavity through the inlet, filling the cavity with the molding resin raw material, and sealing a semiconductor chip and a control element disposed on a main current lead frame and a control lead frame. In this way, the flow velocity of the molding resin raw material flowing to the control wire is reduced.

A semiconductor assembly package is provided. The semiconductor package assembly includes a system-on-chip (SOC) package, a memory package and a heat spreader. The SOC package includes a logic die and a first substrate. The logic die has pads on it. The first substrate is electrically connected to the logic die by the pads. The memory package includes a second substrate and a memory die. The second substrate has a top surface and a bottom surface. The memory die is mounted on the top surface of the second substrate and is electrically connected to the second substrate using bonding wires. The heat spreader is disposed between the SOC package and the memory package, wherein the heat spreader is in contact with a back surface of the logic die away from the pads.

A semiconductor package includes a package board, at least one semiconductor chip disposed on the package board, a molding member disposed on the package board and at least partially surrounding the at least one semiconductor chip, and a heat dissipation member disposed on the at least one semiconductor chip and the molding member. The molding member has first region in which a plurality of uneven structures are disposed, and a second region spaced apart from an external region by the plurality of uneven structures. The plurality of uneven structures protrude to a predetermined height away from the semiconductor chip, the molding member, and the heat dissipation member, and may be formed as a part of the head dissipation member, or formed separately.

A multi-chip unit suitable for chip-level packaging may include multiple IC chips that are interconnected through a metal redistribution structure, and that are directly bonded to an integrated heat spreader. Bonding of the integrated heat spreader to the multiple IC chips may be direct so that no thermal interface material (TIM) is needed, resulting in a reduced bond line thickness (BLT) and lower thermal resistance. The integrated heat spreader may further serve as a structural member of the multi-chip unit, allowing a second side of the redistribution structure to be further interconnected to a host by solder interconnects. The redistribution structure may be fabricated on a sacrificial interposer that may facilitate planarizing IC chips of differing thickness prior to bonding the heat spreader. The sacrificial interposer may be removed to expose the RDL for further interconnection to a substrate without the use of through-substrate vias.

A semiconductor package including a semiconductor chip, an interposer on the semiconductor chip, and a molding layer covering at least a portion of the semiconductor chip and at least a portion of the interposer may be provided. The interposer includes a interposer substrate and a heat dissipation pattern penetrating the interposer substrate and electrically insulated from the semiconductor chip. The heat dissipation pattern includes a through electrode disposed in the interposer substrate and an upper pad disposed on an upper surface of the interposer substrate and connected to the through electrode. The molding layer covers at least a portion of a sidewall of the upper pad and the upper surface of the interposer substrate. At least a portion of an upper surface of the upper pad is not covered by the molding layer.

An object is to provide a technique capable of suppressing generation of a crack in a molding resin and suppressing entry of moisture from the outside. A semiconductor device includes a heat spreader, a semiconductor element provided on an upper surface of the heat spreader, an insulating sheet provided on a lower surface of the heat spreader, a lead frame joined to an upper surface of the semiconductor element via solder, and a molding resin that seals one end side of the lead frame, the semiconductor element, the heat spreader, and the insulating sheet. A hole is formed from an upper surface of the molding resin to a joining surface of the lead frame with the semiconductor element, and the hole is filled with a low Young's modulus resin having a Young's modulus lower than that of the molding resin.

A semiconductor device includes a semiconductor element, a first wiring member, a second wiring member, and a terminal. The semiconductor element includes a first main electrode and a second main electrode on a side opposite from the first main electrode. The first wiring member is connected to the first main electrode. The terminal has a first terminal surface connected to the second main electrode and a second terminal surface. The second terminal has four sides. Two of the four sides are parallel to a first direction intersecting the thickness direction, and other two sides of the four sides are parallel to a second direction perpendicular to the thickness direction and the first direction. The second wiring member is connected to the second terminal surface of the terminal through solder, and has a groove. The groove overlaps one or two of the four sides of the second terminal surface.

An object is to provide a technique capable of suppressing reduction in sticking force of a semiconductor package and a radiation fin in a semiconductor device including the semiconductor package and the radiation fin when the semiconductor package and the radiation fin stick and are fixed to each other by magnetic force. A semiconductor device includes: a semiconductor package; an insulating substrate; a radiation fin; a first fixed part made up of one of a magnetic body and a bond magnet integrally formed with the semiconductor package; and a second fixed part made up of another one of the magnetic body and the bond magnet integrally formed with the radiation fin, wherein the semiconductor package and the radiation fin stick to each other by magnetic force occurring between the first fixed part and the second fixed part.

A semiconductor package includes; laterally stacked semiconductor blocks disposed side by side in a first horizontal direction on a redistribution structure, wherein each semiconductor block among the laterally stacked semiconductor blocks includes laterally stacked semiconductor chips, a heat dissipation plate, and a first molding member on the laterally stacked semiconductor chips.