A microfabrication device is provided. The microfabrication device includes a combined substrate including a first substrate connected to a second substrate, the first substrate having first devices and the second substrate having second devices; fluidic passages formed at a connection point between the first substrate and the second substrate, the connection point including a wiring structure that electrically connects first devices to second devices and physically connects the first substrate to the second substrate; dielectric fluid added to the fluidic passages; and a circulating mechanism configured to circulate the dielectric fluid through the fluidic passages to transfer heat.

In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.

In one embodiment, the disclosure relates to a system of stacked and connected layers of circuits that includes at least one pair of adjacent layers having very few physical (electrical) connections. The system includes multiple logical connections. The logical interconnections may be made with light transmission. A majority of physical connections may provide power. The physical interconnections may be sparse, periodic and regular. The exemplary system may include physical space (or gap) between the a pair of adjacent layers having few physical connections. The space may be generally set by the sizes of the connections. A constant flow of coolant (gaseous or liquid) may be maintained between the adjacent pair of layers in the space.

Implementations of a semiconductor package may include one or more power semiconductor die included in a die module; a first heat sink directly coupled to one or more source pads of the die module; a second heat sink directly coupled to one or more drain pads of the die module; a gate contact coupled with one or more gate pads of the die module; and a coating coupled directly to the die module. The gate contact may be configured to extend through an immersion cooling enclosure.

Implementations of a semiconductor package may include one or more power semiconductor die included in a die module; a first heat sink directly coupled to one or more source pads of the die module; a second heat sink directly coupled to one or more drain pads of the die module; a gate contact coupled with one or more gate pads of the die module; and a coating coupled directly to the die module. The gate contact may be configured to extend through an immersion cooling enclosure.

Fluid replacement structures used in immersion cooling tanks can include various enhancements to make them functional beyond simply taking up space. For example, the density of fluid replacement structures can be variable to assist with buoyancy control. As another example, fluid replacement structures can be designed to enable vaporized working fluid to be directed to a desired location. As another example, fluid replacement structures can include emergency cooling features, such as different substances that cause an endothermic reaction to occur when they are mixed together. The substances can be separated by a membrane that melts when the temperature reaches a certain point. As another example, a fluid replacement structure can provide structural support for an immersion cooling tank when negative pressure operations are performed. Fluid replacement structures can also include alignment features, lifting features, locking features, mating guides, fiducial markers, or the like.

Disclosed is a semiconductor module comprising a module substrate having a top surface and a bottom surface that are opposite to each other, a plurality of semiconductor packages on the top surface of the module substrate and arranged in a first direction parallel to the top surface of the module substrate, and a clip structure on the top surface of the module substrate and spaced apart from the plurality of semiconductor packages in the first direction. The clip structure includes a body part on the top surface of the module substrate and spaced apart from the plurality of semiconductor packages in the first direction, and a connection part that extends from the body part across a lateral surface of the module substrate onto the bottom surface of the module substrate.

Disclosed is a semiconductor module comprising a module substrate having a top surface and a bottom surface that are opposite to each other, a plurality of semiconductor packages on the top surface of the module substrate and arranged in a first direction parallel to the top surface of the module substrate, and a clip structure on the top surface of the module substrate and spaced apart from the plurality of semiconductor packages in the first direction. The clip structure includes a body part on the top surface of the module substrate and spaced apart from the plurality of semiconductor packages in the first direction, and a connection part that extends from the body part across a lateral surface of the module substrate onto the bottom surface of the module substrate.

A method includes coating, via chemical vapor deposition, electronics disposed on a printed circuit board (PCB) with an electrical insulation coating of between one micron to 25 microns. The method further include depositing, on the electrical insulation coating, a metallic nano-layer comprising a porous metallic nano-structure. The method further includes, after the coating and the depositing, immersing the PCB in a water-based fluid to cool the electronics while the electronics are powered on.

A direct to chip cooling film for two-phase cooling. The film includes a dielectric layer having a first surface for attachment to a cold plate or circuits and having a second surface. A metal layer is on the second surface of the dielectric layer with a pattern of features on a side opposite the dielectric layer. This surface pattern provides increased surface area and multiple nucleation sites for bubbles formation for two-phase cooling. The features can also include metal nodules to further enhance the nucleation.