A method of forming a semiconductor device includes providing a substrate that comprises a metal region, forming an encapsulant body of electrically insulating material on an upper surface of the metal region, forming an opening in the encapsulant body, and inserting a press-fit connector into the opening, wherein after inserting the press-fit connector into the opening, the press-fit connector is securely retained to the substrate and an interfacing end of the press-fit connector is electrically accessible.

A semiconductor device includes: a semiconductor module including a switching device, a first wiring connected to the switching device, a second wiring positioned adjacent to the first wiring and generating induced electromotive force according to a change in an electric current flowing in the first wiring, and a sealing material sealing the switching device, the first wiring and the second wiring, wherein both of one end and the other end of the second wiring are exposed from the sealing material; a substrate including a GND electrode connected to the one end and on which the semiconductor module is mounted; and a diode rectifying the induced electromotive force output from the other end.

A semiconductor package is provided. The semiconductor package includes: a first semiconductor chip including a first bonding structure; , a first front-end level layer including a first integrated circuit device; a first sub-back-end level layer including a plurality of first metal wire layers, an input and output device level layer including a two-dimensional input and output device, and a second sub-back-end level layer including a plurality of second metal wire layers electrically connected to the first integrated circuit device and the two-dimensional input and output device. The semiconductor package also includes a second semiconductor chip including a bonding structure that is bonded to the first bonding structure; a second front-end level layer including a second integrated circuit device, and a second back-end level layer including a plurality of third metal wire layers electrically connected to the second integrated circuit device.

A semiconductor package includes: a first substrate having a first metallized side; a semiconductor die attached to the first metallized side of the first substrate at a first side of the die, a second side of the die opposite the first side being covered by a passivation, the passivation having a first opening that exposes at least part of a first pad at the second side of the die; a thermally and electrically conductive spacer attached to the part of the first pad that is exposed by the first opening in the passivation, the spacer at least partly overhanging the passivation along at least one side face of the semiconductor die; a second substrate having a first metallized side attached to the spacer at an opposite side of the spacer as the semiconductor die; and an encapsulant encapsulating the semiconductor die and the spacer. Additional spacer embodiments are described.

In the present invention, in order to reduce parasitic inductances of a gate line and a source line of a power module to reduce a current deviation (current balancing) which is a problem when the power module composed of a plurality of parallel chips is driven, in a power module including a plurality of power semiconductor chips connected to gate lines and source lines extending from gate pins and source pins in parallel by different distances, a current area of each of the gate lines and the source lines connected to chips other than a first chip closest to the gate pin and the source pin is formed larger than a current area of each of the gate line and the source line connected to the first chip.

A semiconductor device includes: a metal block; a semiconductor element fixed to an upper surface of the block with a first joining material; a main terminal fixed to an upper surface of the element with a second joining material; a signal terminal electrically connected to the element; and a mold resin covers the element, the first and second joining materials, a part of the block, of the main and signal terminals. In the element, a current flows in a longitudinal direction. A lower surface of the block is exposed from the resin. The main and the signal terminals are exposed from a side surface of the resin. The main terminal has a first portion in the resin, a second portion continuous with the first portion and bent downward outside the resin, and a third portion continuous with the second portion and substantially parallel to a lower surface of the resin.

A low parasitic inductance power module featuring staggered interleaving conductive members, including: at least one base extending in a length direction; a substrate on which at least one input bus bar and at least one output bus bar are provided; a first unit including a first circuit base portion disposed on the base in a width direction, a plurality of first power devices being disposed on the first circuit base portion, each first power device having a first current input end and a first current output end which are parallel connected, the first current input end or the first current output end being conducted to the first circuit base portion; and a second unit. The units are serially-connected to the bus bars via input conductive members and output conductive members arrayed in a staggered interleaving mode, whereby to create individual inductances counteracting with each other, reducing overall parasitic inductance.

A semiconductor device, having a substrate including an insulating plate and a circuit board provided on a front surface of the insulating plate. The circuit board has a first disposition area and a second disposition area with a gap therebetween, and a groove portion, of which a longitudinal direction is parallel to the gap, formed in the gap. The semiconductor device further includes a first semiconductor chip and a second semiconductor chip located on the circuit board in the first disposition area and the second disposition area, respectively, and a blocking member located in the gap across the groove portion in parallel to the longitudinal direction in a plan view of the semiconductor device.

Provided is a semiconductor module that can improve the insulation properties at terminals to which electric power is supplied. A semiconductor module includes a negative electrode terminal connected to a negative electrode side of direct current power; a positive electrode terminal disposed above the negative electrode terminal and connected to a positive electrode side of the direct current power in a state where an exposed portion of the negative electrode terminal including one end of the negative electrode terminal is exposed; an insulating sheet disposed between the negative electrode terminal and the positive electrode terminal for insulation between the negative electrode terminal and the positive electrode terminal in a state where an exposed portion of the insulating sheet is exposed between the one end of the negative electrode terminal and one end of the positive electrode terminal; and a first dielectric portion formed to cover at least a corner of the one end of the positive electrode terminal, the corner being in contact with the insulating sheet.

Embodiments disclosed herein include electronic packages with improved thermal performance. In an embodiment, the electronic package comprises a first package substrate, a first die stack over the first package substrate, and a heat spreader over the first die stack. In an embodiment, the heat spreader comprises arms that extend out past sidewalls of the first package substrate. In an embodiment, the electronic package further comprises an interposer over and around the heat spreader, where the interposer is electrically coupled to the first package substrate by a plurality of interconnects. In an embodiment, the electronic package further comprises a second package substrate over the interposer, and a second die over the second package substrate.