SEMICONDUCTOR DEVICE

Abstract

A semiconductor device includes: a metal block; a semiconductor element fixed to an upper surface of the block with a first joining material; a main terminal fixed to an upper surface of the element with a second joining material; a signal terminal electrically connected to the element; and a mold resin covers the element, the first and second joining materials, a part of the block, of the main and signal terminals. In the element, a current flows in a longitudinal direction. A lower surface of the block is exposed from the resin. The main and the signal terminals are exposed from a side surface of the resin. The main terminal has a first portion in the resin, a second portion continuous with the first portion and bent downward outside the resin, and a third portion continuous with the second portion and substantially parallel to a lower surface of the resin.

Claims

1. A semiconductor device comprising: a metal block; a semiconductor element that is fixed to an upper surface of the metal block with a first joining material and in which a current flows in a longitudinal direction; a main terminal fixed to an upper surface of the semiconductor element with a second joining material; a signal terminal electrically connected to the semiconductor element; and a mold resin that covers the semiconductor element, the first joining material, and the second joining material, and covers a part of the metal block, a part of the main terminal, and a part of the signal terminal, wherein a lower surface of the metal block is exposed from the mold resin, the main terminal and the signal terminal are each exposed from a side surface of the mold resin, and the main terminal has a first portion in the mold resin, a second portion continuous with the first portion and bent downward outside the mold resin, and a third portion continuous with the second portion and substantially parallel to a lower surface of the mold resin.

2. The semiconductor device according to claim 1, wherein the signal terminal has a shape bent upward outside the mold resin.

3. The semiconductor device according to claim 1, wherein the metal block is copper or a copper alloy, and is thicker than the main terminal.

4. The semiconductor device according to claim 1, wherein a thickness of the metal block is equal to or more than twice a thickness of the main terminal.

5. The semiconductor device according to claim 1, further comprising an insulating substrate having a metal base, an insulating layer provided on the metal base, and a plurality of circuit patterns provided on the insulating layer, wherein the main terminal is fixed to a certain circuit pattern among the plurality of circuit patterns with a third joining material, and the lower surface of the metal block is fixed to another circuit pattern among the plurality of circuit patterns with a fourth joining material.

6. The semiconductor device according to claim 1, further comprising: an insulating substrate having a metal base, an insulating layer provided on the metal base, and a plurality of circuit patterns provided on the insulating layer; an auxiliary insulating layer provided on a partial upper surface of each of the circuit patterns; and an auxiliary circuit pattern provided on the auxiliary insulating layer, wherein the main terminal is fixed to the auxiliary circuit pattern with a fifth joining material, and the lower surface of the metal block is fixed to the circuit pattern with a fourth joining material.

7. The semiconductor device according to claim 1, wherein the lower surface of the metal block reaches below the lower surface of the mold resin.

8. The semiconductor device according to claim 1, wherein the lower surface of the mold resin has a groove along an outer edge of the metal block.

9. A semiconductor device comprising: a metal block; a semiconductor element that is fixed to an upper surface of the metal block with a first joining material and in which a current flows in a longitudinal direction; a main terminal fixed to an upper surface of the semiconductor element with a second joining material; a signal terminal electrically connected to the semiconductor element; and a mold resin that covers the semiconductor element, the first joining material, and the second joining material, and covers a part of the metal block, a part of the main terminal, and a part of the signal terminal, wherein a lower surface of the metal block is exposed from the mold resin, the main terminal and the signal terminal are each exposed from a side surface of the mold resin, and the signal terminal has a fourth portion in the mold resin, a fifth portion continuous with the fourth portion and bent downward outside the mold resin, and a sixth portion continuous with the fifth portion and substantially parallel to a lower surface of the mold resin.

10. The semiconductor device according to claim 1, wherein the main terminal is exposed from a plurality of side surfaces of the mold resin.

11. The semiconductor device according to claim 5, wherein a partial surface of each of the plurality of circuit patterns is covered with an insulating resin.

12. The semiconductor device according to claim 1, wherein the semiconductor element is formed of a wide-bandgap semiconductor.

13. The semiconductor device according to claim 12, wherein the wide-bandgap semiconductor is silicon carbide, a gallium nitride-based material, or diamond.

14. The semiconductor device according to claim 9, wherein the main terminal is exposed from a plurality of side surfaces of the mold resin.

15. The semiconductor device according to claim 9, wherein the semiconductor element is formed of a wide-bandgap semiconductor.

16. The semiconductor device according to claim 15, wherein the wide-bandgap semiconductor is silicon carbide, a gallium nitride-based material, or diamond.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment.

[0015] FIG. 2 is a perspective view of the semiconductor device.

[0016] FIG. 3 is a perspective view of the semiconductor device.

[0017] FIG. 4 is a diagram illustrating the relationship between the thickness of the metal block and the thermal resistance.

[0018] FIG. 5 is a cross-sectional view of a semiconductor device according to a third embodiment.

[0019] FIG. 6 is a perspective view of the semiconductor device.

[0020] FIG. 7 is a cross-sectional view of a semiconductor device according to a fourth embodiment.

[0021] FIG. 8 is a cross-sectional view of a semiconductor device according to a fifth embodiment.

[0022] FIG. 9 is a cross-sectional view of a semiconductor device according to a sixth embodiment.

[0023] FIG. 10 is a cross-sectional view of a semiconductor device according to a seventh embodiment.

[0024] FIG. 11 is a perspective view of the semiconductor device.

[0025] FIG. 12 is a perspective view of the semiconductor device.

[0026] FIG. 13 is a plan view of a semiconductor device according to an eighth embodiment.

[0027] FIG. 14 is a cross-sectional view of a semiconductor device according to a ninth embodiment.

DESCRIPTION OF EMBODIMENTS

[0028] A semiconductor device according to an embodiment of the present disclosure will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and the repetition of the description may be omitted.

First Embodiment

[0029] FIG. 1 is a cross-sectional view of a semiconductor device 10 according to a first embodiment. The semiconductor device 10 includes a metal block 12. As the metal block 12, a material having high thermal conductivity, low electrical resistivity, and low cost can be adopted. The metal block 12 is formed of, for example, copper or a copper alloy. A semiconductor element 16 is fixed to the upper surface of the metal block 12 with a first joining material 14a. The semiconductor element 16 is an element in which a current flows in the longitudinal direction. According to one example, the semiconductor element 16 is an insulated-gate bipolar transistor (IGBT) having a collector on the lower surface and an emitter and a base on the upper surface. A main current flows into the collector and flows out of the emitter. According to another example, the semiconductor element 16 is a metal-oxide-semiconductor field-effect transistor (MOSFET), and the main current flows into the drain and flows out of the source. As the semiconductor element 16, an arbitrary element in which the main current flows in the longitudinal direction can be adopted.

[0030] A main terminal 18 is fixed to the upper surface of the semiconductor element 16 with a second joining material 14b. A wire 20 made of aluminum or the like is connected to the upper surface of the semiconductor element 16. By the connection of the wire 20 to the signal terminal 22, the signal terminal 22 is electrically connected to the semiconductor element 16.

[0031] As the first joining material 14a, the second joining material 14b, and joining materials to be described later, solder or a brazing material such as silver can be used. For example, by reflow processing of the brazing material, joining using the joining material can be performed. According to one example, the materials of the main terminal 18 and the signal terminal 22 may be copper or a copper alloy.

[0032] The above structure is integrally sealed with a mold resin 30. Specifically, the mold resin 30 covers the semiconductor element 16, the first joining material 14a, and the second joining material 14b, and covers a part of the metal block 12, a part of the main terminal 18, and a part of the signal terminal 22. The lower surface of the metal block 12 is exposed from the mold resin 30. The metal block 12 is exposed only from the lower surface of the mold resin 30. The exposed metal block 12 serves as an energizing path for a collector current.

[0033] The main terminal 18 and the signal terminal 22 are exposed from the side surfaces of the mold resin 30. The main terminal 18 has a first portion 18a in the mold resin 30, a second portion 18b continuous with the first portion 18a and bent downward outside the mold resin 30, and a third portion 18c continuous with the second portion 18b and substantially parallel to the lower surface of the mold resin 30. According to one example, the main terminal 18 is bent downward outside the mold resin 30 and includes the third portion 18c that is a flat portion at substantially the same height as the back surface of the mold resin 30. The main terminal 18 provides an energizing path for an emitter current.

[0034] According to one example, the signal terminal 22 is bent upward outside the mold resin 30. As a result, the signal terminal 22 has a shape bent upward outside the mold resin 30.

[0035] FIG. 2 is a perspective view of the semiconductor device before the mold resin 30 is formed. In FIG. 2, the wire 20 of FIG. 1 is omitted. The main terminal 18 is in contact with the emitters of two semiconductor elements 16. FIG. 2 illustrates that the metal block 12 is thicker than the main terminal 18. The material of the metal block 12 is, for example, copper or a copper alloy. The main terminal 18 is a plate-like frame.

[0036] FIG. 3 is a perspective view of the semiconductor device 10 of FIG. 1. The main terminal 18 and all the signal terminals 22 are exposed from the side surfaces of the mold resin 30. The semiconductor device 10 described with reference to FIGS. 1 to 3 may be used, for example, for an inverter, which controls a motor of an electric vehicle, electric train, or the like, or for regenerative converter.

[0037] In the case of attaching a known resin-sealed semiconductor device to a cooler, a minute gap between the lower surface of the package and the cooler has been filled with heat-dissipating grease to enhance heat dissipation, and a spring or the like has been used to press the resin package against the cooler from the upper surface of the resin package.

[0038] In contrast, in the semiconductor device according to the first embodiment, as a result of forming the main terminal 18 into the shape described above, both the main terminal 18 and the metal block 12 can be connected to an insulating substrate by solder or the like. Therefore, the use of the semiconductor device according to the first embodiment eliminates the need for a pressing mechanism such as a spring and facilitates assembly.

[0039] Moreover, in the semiconductor device 10 according to the first embodiment, the metal block 12 through which the collector current flows is exposed only from the back surface of the mold resin 30, and the main terminal 18 through which the emitter current flows and the signal terminal 22 for transmitting and receiving signals are exposed only from the side surfaces of the mold resin 30, whereby the insulation distance can be ensured. Therefore, it is possible to reduce the size as compared to a semiconductor element provided with a collector potential frame.

[0040] Further, the provision of the metal block 12 reduces unnecessary wiring routing, so that the inductance can be reduced. The metal block 12 can diffuse heat generated from the semiconductor element 16 to efficiently dissipate the heat.

[0041] In a case where a die pad DP1 described in JP 2013-074264 A is formed using a frame, in the manufacturing process, a plurality of resin molds are connected by the frame, and hence the frame needs to be cut. Thus, as illustrated in FIG. 10 of JP 2013-074264, the die pad DP1 to serve as a collector potential is exposed on the side surface of the resin package. In this case, the package becomes large in order to ensure the insulation distance between a main terminal to serve as an emitter potential and the die pad DP1 to serve as the collector potential. Moreover, since the die pad DP1 is the frame, it is difficult to ensure a sufficient thickness for improving heat dissipation. In the semiconductor device 10 of the first embodiment, these problems are reduced by exposing the metal block 12 thicker than the main terminal 18 only from the back surface of the mold resin 30, and exposing the main terminal 18 only from the side surface of the mold resin 30.

[0042] The modifications, alternations, or alternatives described in the first embodiment can be applied to semiconductor devices according to the following embodiments. The semiconductor devices according to the following embodiments will be described mainly in terms of the difference from the first embodiment.

Second Embodiment

[0043] In a semiconductor device according to a second embodiment, the thickness of the metal block 12 is made equal to or more than twice the thickness of the main terminal 18. FIG. 4 is a diagram illustrating a result of calculating the relationship between the thickness of the metal block 12 and the thermal resistance by the finite element method. In the process of increasing the thickness of the metal block 12 to about 2 mm, a rapid decrease in thermal resistance is observed. When the thickness of the metal block 12 is increased to exceed 2 mm, the value of the thermal resistance saturates gradually. The main terminal 18 may have a thickness of about 1 mm or less in consideration of workability and assembling. When the current is small, the thickness of the main terminal 18 can be reduced, and the thickness of the metal block 12 can also be reduced.

[0044] As described above, the thickness of the metal block 12 is correlated with the thermal resistance, and with an increase in the thickness, the effect increases and tends to saturate gradually. Making the thickness of the metal block 12 equal to or more than twice the thickness of the main terminal 18 is effective in reducing the thermal resistance.

Third Embodiment

[0045] FIG. 5 is a cross-sectional view of a semiconductor device according to a third embodiment. The semiconductor device includes an insulating substrate 50. The insulating substrate 50 has a metal base 50b, an insulating layer 50a provided on the metal base 50b, and a plurality of circuit patterns 50c provided on the insulating layer 50a. The main terminal 18 is fixed to a left circuit pattern 50c of the plurality of circuit patterns 50c with a third joining material 52. The lower surface of the metal block 12 is fixed to a right circuit pattern 50c of the plurality of circuit patterns 50c with a fourth joining material 54.

[0046] An electrode 60 is fixed to the left circuit pattern 50c with a joining material 56. An electrode 62 is fixed to the right circuit pattern 50c with a joining material 58. A part of each of the electrodes 60, 62 is mounted on an upper surface of a package 64.

[0047] FIG. 6 is a view illustrating the inside of the semiconductor device of FIG. 5. For facilitating the understanding, a semiconductor device sealed with the mold resin 30 and a semiconductor device not sealed with the mold resin are illustrated. Both the metal block 12 and the main terminal 18 are joined to the circuit pattern 50c of the insulating substrate 50.

[0048] The circuit pattern 50c can be easily formed by, for example, etching, so that circuit formation and assembly are easier than in the case of busbar wiring. The metal base 50b of the insulating substrate 50 promotes cooling of a wiring portion as compared to the busbar wiring. When the wiring portion is cooled, wiring resistance is reduced, so that the cross-sectional area of the wiring portion can be reduced.

[0049] In the semiconductor device according to the third embodiment, heat generated from the semiconductor element 16 diffuses to the metal block 12 and is conducted to the metal base 50b via the insulating layer 50a. The insulating layer 50a when the insulating substrate 50 is a resin insulating substrate has a lower thermal conductivity than that of ceramic such as aluminum nitride or silicon nitride, but can also obtain a thermal resistance equivalent to that when a ceramic substrate is used due to the thermal diffusion effect of the metal block 12. In the case of setting the semiconductor device on a cooling fin with grease or the like, it has been necessary to press the semiconductor device with a spring or the like. However, in the case of the developed product, the joining material such as the brazing material is used, and hence peripheral parts such as a spring are not necessary. Since the main circuit is wired using the circuit pattern 50c of the insulating substrate 50, and the metal base 50b is disposed with the thin insulating layer 50a interposed therebetween, the inductance can be reduced.

Fourth Embodiment

[0050] FIG. 7 is a cross-sectional view of a semiconductor device according to a fourth embodiment. As in the third embodiment, the semiconductor device includes an insulating substrate 50 having a metal base 50b, an insulating layer 50a provided on the metal base 50b, and a plurality of circuit patterns 50c provided on the insulating layer 50a. An auxiliary insulating layer 80 is provided on a partial upper surface of the circuit pattern 50c. An auxiliary circuit pattern 82 is provided on the auxiliary insulating layer 80.

[0051] The main terminal 18 is fixed to the auxiliary circuit pattern 82 with a fifth joining material 55. The lower surface of the metal block 12 is fixed to the circuit pattern 50c with a fourth joining material 54.

[0052] As illustrated in FIG. 7, the third portion 18c including the flat surface of the main terminal 18 is located above the back surface of the metal block 12. The auxiliary insulating layer 80 and the auxiliary circuit pattern 82 are disposed to be laminated on the circuit pattern 50c to which the metal block 12 is joined, and the main terminal 18 is joined to the auxiliary circuit pattern 82. With such a configuration, it is possible to provide the emitter pattern and the collector pattern in parallel while bringing the patterns close to each other, thereby reducing the inductance.

Fifth Embodiment

[0053] FIG. 8 is a cross-sectional view of a semiconductor device according to a fifth embodiment. The lower surface of the metal block 12 reaches below the lower surface of the mold resin 30. FIG. 8 illustrates that the lower surface of the metal block 12 is located at a distance L1 below the lower surface of the mold resin 30. In other words, the exposed portion of the metal block 12 protrudes from the back surface of the mold resin 30. According to the semiconductor device of the fifth embodiment, the joining material such as a solder fillet can be formed on the side surface of the metal block 12, thus improving the reliability of the joint. The reliability of the joint is, for example, durability under temperature stress.

Sixth Embodiment

[0054] FIG. 9 is a cross-sectional view of a semiconductor device according to a sixth embodiment. On the lower surface of the mold resin 30, a groove 30a is provided along the outer edge of the metal block 12. In a bottom view, the groove 30a surrounds the exposed portion of the metal block 12, and is provided on the back surface of the mold resin 30. For example, when the joining material under the metal block 12 is thinned in order to lower the thermal resistance of the semiconductor element 16, there is a possibility that excess joining material flows out to cause a short circuit between the circuit patterns. By recovering such excess joining material in the groove 30a, the outflow of the excess joining material can be prevented.

Seventh Embodiment

[0055] FIG. 10 is a cross-sectional view of a semiconductor device according to a seventh embodiment. A signal terminal 22 has a fourth portion 22a in the mold resin 30, a fifth portion 22b continuous with the fourth portion 22a and bent downward outside the mold resin 30, and a sixth portion 22c continuous with the fifth portion 22b and substantially parallel to the lower surface of the mold resin 30.

[0056] As a result of forming the signal terminal 22 according to the seventh embodiment into the shape described above, the signal terminal 22 can be connected to a circuit pattern, and the circuit pattern can be used as signal wiring. Therefore, for example, at the time of mounting a plurality of semiconductor devices sealed with a mold resin on the same insulating substrate, a plurality of signal terminals can be externally connected by one connector.

[0057] In the example of the seventh embodiment, since both the signal terminal 22 and the main terminal 18 are bent downward outside the mold resin 30, the signal terminal 22 and the main terminal 18 can be connected to the insulating substrate.

[0058] FIG. 11 is a perspective view of a semiconductor device before the mold resin is formed. The main terminal 18 and a plurality of signal terminals 22 are provided. The wire 20 is omitted. FIG. 12 is a perspective view of the semiconductor device of FIG. 10. The main terminals 18 and the signal terminals 22 are all exposed to the outside from the side surfaces of the mold resin 30.

Eighth Embodiment

[0059] FIG. 13 is a plan view of a semiconductor device according to an eighth embodiment. The main terminal 18 is exposed from a plurality of side surfaces of the mold resin 30. In the example of FIG. 13, the main terminal 18 is exposed from the side surfaces of the mold resin 30 in three exposed portions 18A, 18B, 18C. According to another example, two exposed portions may be provided, and the exposed portions may be exposed from two side surfaces of the mold resin. According to still another example, four exposed portions may be provided, and the exposed portions are exposed from the four side surfaces of the mold resin. The plurality of exposed portions of the main terminal 18 may each include the second portion 18b and the third portion 18c as illustrated in FIG. 1 and the like.

[0060] Exposing the main terminals 18 from a plurality of side surfaces of the mold resin 30 improves the degree of freedom in the layout of the circuit pattern of the insulating substrate. Increasing the degree of freedom in the layout of the circuit pattern enables a reduction in the size of the device.

Ninth Embodiment

[0061] FIG. 14 is a cross-sectional view of a semiconductor device according to a ninth embodiment. A partial surface of the circuit pattern 50c is covered with an insulating resin 90. When there are a plurality of circuit patterns 50c, partial surfaces of the plurality of circuit patterns 50c are covered with the insulating resin 90. When the auxiliary circuit pattern 82 is present, a partial surface of the auxiliary circuit pattern 82 is also covered with the insulating resin 90. The insulating resin 90 is, for example, silicone gel. The insulating resin 90 improves the insulation between the circuit pattern and another circuit pattern, so that the interval between the patterns can be narrowed. Reducing the interval between the patterns enables a reduction in the size of the device.

[0062] The semiconductor elements 16 in all the above embodiments may each be formed of a wide-bandgap semiconductor having a larger bandgap than silicon. The wide-bandgap semiconductor is excellent in withstand voltage properties and the like, thus enabling a reduction in the size of the semiconductor device. The wide-bandgap semiconductor includes, for example, silicon carbide, gallium nitride-based materials, or diamond. Particularly, in the present disclosure, the material and thickness of the metal block 12 on which the semiconductor element is mounted are set as described above to improve heat dissipation, so that the area of the semiconductor element formed with a wide bandgap can be reduced. Therefore, it is suitable for cost reduction.

[0063] Note that the features of the semiconductor devices according to the above embodiments can be combined.

REFERENCE SIGNS LIST

[0064] 10 semiconductor device, 12 metal block, 14a first joining material, 14b second joining material, 16 semiconductor element, 18 main terminal, 18a first portion, 18b second portion, 18c third portion, 20 wire, 22 signal terminal, 30 mold resin