An electronic device includes a first surface and a second surface opposite the first surface and intended to connect a first electronic component to a second electronic component located on the first surface by at least one conductor track, the conductor track including a plurality of sections disposed one after the other in such a way as to form the conductor track, each section being constituted of a superconducting material chosen in such a way as to form with the section that follows it, if such a section exists, and the section that precedes it, if such a section exists, an acoustic mismatching interface (or Kapitza interface).

A superconducting device according to an example embodiment includes: a superconducting chip; an interposer on which the superconducting chip is mounted; a socket that is arranged to face the interposer and includes a movable pin and a housing supporting the movable pin; and a board that is arranged to face the socket and includes a connector serving as an input/output with respect to the outside. In the board, one end of a terminal of a via hole is electrically connected to one end of a terminal of the movable pin, and a hole diameter of the via hole is smaller than a diameter of a tip portion of the movable pin connected to the via hole.

A cryogenic multilayer interconnect structure has a substrate including a molybdenum layer, a first insulating layer on the substrate and a first superconducting layer on the first insulating layer. The molybdenum layer has a coefficient of thermal expansion (CTE) that is well matched with the CTE of cryogenic electronic chips that are to be attached to the cryogenic multilayer interconnect structure. The substrate may be a copper clad molybdenum substrate that provide the CTE advantages provided by the molybdenum layer while also providing an increased thermal conductivity to improve the dissipation of heat generated by cryogenic electronic chips coupled to the substrate.

A quantum device according to an example embodiment includes: a quantum chip with a first surface and a second surface located on a side opposite to the first surface, in the quantum chip, at least a part of a qubit circuit being provided on the second surface; a first interposer with a third surface and a fourth surface located on a side opposite to the third surface, the first interposer being connected to the quantum chip in such a manner that the second surface of the quantum chip is opposed to the third surface of the first interposer; and a second interposer with a fifth surface and a sixth surface located on a side opposite to the fifth surface, the second interposer being connected to the first interposer in such a manner that the fourth surface of the first interpose is opposed to the fifth surface of the second interposer.

Techniques regarding qubit chip assemblies are provided. For example, one or more embodiments described herein can include an apparatus that can comprise a qubit chip positioned on an interposer chip. The apparatus can also comprise an electrical connector in direct contact with the interposer chip. The electrical connector can establish an electrical communication between a wire and a contact pad of the interposer chip that is coupled to the qubit chip.

An integration structure for connecting a plurality of semiconductor devices, includes a substrate, a first face and a second face for receiving the semiconductor devices. At the first surface, at least one routing level includes at least one non-superconducting conductive routing track of a conductive material; and at least one superconducting routing track of a superconducting material. At the second surface, at least one routing level includes at least one non-superconducting conductive routing track of a conductive material; and at least one superconducting routing track of a superconducting material. The integration structure includes at least one non-superconducting conductive via connecting a non-superconducting conductive routing track of the first face to a non-superconducting conductive track of the second face and/or at least one superconducting via connecting a superconducting routing track of the first face to a superconducting track of the second face.

A quantum device (100) includes an interposer (112), a quantum chip (111) mounted on the interposer (112), and a shield part (150) provided so as to surround a quantum circuit region of the interposer (112) and the quantum chip (111). Accordingly, the quantum device (100) is able to prevent interference in the quantum circuit region due to exogenous noise.

A quantum device capable of effectively cooling a quantum chip and an area (e.g., a space) therearound is provided. A quantum device 1 includes a quantum chip 10 and an interposer 20 on which the quantum chip 10 is located. The interposer 20 includes an interposer substrate 22 and an interposer wiring layer 30. The interposer wiring layer 30 is disposed on a surface 22a of the interposer substrate 22 on a side on which the quantum chip 10 is located. The interposer wiring layer 30 includes, in at least a part thereof, a superconducting material layer 32 formed of a superconducting material and a non-superconducting material layer 34 formed of a non-superconducting material.

A quantum device (100) includes: an interposer (112); a quantum chip (111); a first connection part (130) that is provided between the interposer (112) and the quantum chip (111) and electrically connects a wiring layer of the interposer (112) to a wiring layer of the quantum chip (111); and a second connection part (140) that is provided on a main surface of the interposer (112) where the first connection part (130) is arranged and is connected to a cooling plate (115).

A quantum device according to an example embodiment includes a quantum chip 10, and an interposer 20 on which the quantum chip 10 is mounted, in which the interposer 20 includes a conductive wiring line CL1 electrically connected to the quantum chip 10, a mounting surface 21 of the interposer 20 on which the quantum chip 10 is mounted or an opposite surface 22 opposite to the mounting surface 21 includes a first area AR11 and a second area AR12 different from the first area AR11 as viewed in a direction perpendicular to the mounting surface 21 or the opposite surface 22, the conductive wiring line CL1 is disposed in the first area AR11 on the mounting surface 21 or the opposite surface 22, and a movable member 60 is in contact with the second area AR12 of the interposer 20.