A semiconductor package includes a semiconductor package includes first, second, third and fourth semiconductor chips sequentially stacked on one another. Each of the first, second, third and fourth semiconductor chips includes a first group of bonding pads and a second group of bonding pads alternately arranged in a first direction and input/output (I/O) circuitry selectively connected to the first group of bonding pads respectively. Each of the first, second and third semiconductor chips includes a first group of through electrodes electrically connected to the first group of bonding pads and a second group of through electrodes electrically connected to the second group of bonding pads.

A cross-point memory includes a plurality of memory devices, with each device comprising a memory layer between first and second address lines. In one preferred embodiment, the memory layer comprises an OTS (Ovonic Threshold Switch) film and an antifuse film. In another preferred embodiment, the memory layer comprises an OTS film having a first switch voltage (i.e. forming voltage V.sub.form) greater than all subsequent switch voltages (i.e. threshold voltage V.sub.th). The cross-point memory is preferably a three-dimensional one-time-programmable memory (3D-OTP), including horizontal 3D-OTP and vertical 3D-OTP

A method for integrating transistors and anti-fuses on a device includes epitaxially growing a semiconductor layer on a substrate and masking a transistor region of the semiconductor layer. An oxide is formed on an anti-fuse region of the semiconductor layer. A semiconductor material is grown over the semiconductor layer to form an epitaxial semiconductor layer in the transistor region and a defective semiconductor layer in the anti-fuse region. Transistor devices in the transistor region and anti-fuse devices in the anti-fuse region are formed wherein the defective semiconductor layer is programmable by an applied field.

A method of manufacturing an anti-fuse device includes forming an anti-fuse structure on a substrate, forming a first transistor at a first position away from the anti-fuse device in a first direction, and forming a second transistor at a second position away from the anti-fuse device in a second direction opposite the first direction. Forming the anti-fuse structure includes forming first and second S/D structures in an active area, the first transistor includes the first S/D structure, and the second transistor includes the second S/D structure. The method includes constructing a first electrical connection between gate structures of the first and second transistors and a second electrical connection between a third S/D structure of the first transistor and a fourth S/D structure of the second transistor.

The present application discloses a semiconductor device with a programmable unit and a method for fabricating the semiconductor device. The semiconductor device including a substrate, a bottom conductive layer positioned in the substrate, a first gate structure including a first gate dielectric layer positioned on the bottom conductive layer, a first work function layer positioned on the first gate dielectric layer, and a first filler layer positioned on the first work function layer, a second gate structure including a second gate dielectric layer positioned on the bottom conductive layer and spaced apart from the first gate dielectric layer, a second work function layer positioned on the second gate dielectric layer, and a second filler layer positioned on the second work function layer, a conductive plug electrically coupled to the bottom conductive layer, and a top conductive layer electrically coupled to the first gate structure and the second gate structure.

A memory device includes a first transistor. The first transistor includes one or more first semiconductor nanostructures spaced apart from one another along a first direction. Each of the one or more first semiconductor nanostructures has a first width along a second direction perpendicular to the first direction. The memory device also includes a second transistor coupled to the first transistor in series. The second transistor includes one or more second semiconductor nanostructures spaced apart from one another along the first direction. Each of the one or more second semiconductor nanostructures has a second, different width along the second direction.

The present disclosure provides a semiconductor device with a fuse structure and an anti-fuse structure and a method for forming the semiconductor device. The semiconductor device includes a first dielectric layer disposed over a semiconductor substrate, and a first electrode disposed over the first dielectric layer. The semiconductor device also includes a fuse link disposed over the first electrode, and a second electrode disposed over the fuse link. The semiconductor device further includes a third electrode disposed adjacent to the first electrode, and a second dielectric layer separating the first electrode from the first dielectric layer and the third electrode. The first electrode, the fuse link, and the second electrode form a fuse structure, and the first electrode, the third electrode, and a portion of the second dielectric layer between the first electrode and the third electrode form an anti-fuse structure.

A one-time programmable (OTP) memory cell includes a substrate having a first conductivity type and having an active area surrounded by an isolation region, a transistor disposed on the active area, and a capacitor disposed on the active area and electrically coupled to the transistor. The capacitor comprises a diffusion region of a second conductivity type in the substrate, a metallic film in direct contact with the active area, a capacitor dielectric layer on the metallic film, and a metal gate surrounded by the capacitor dielectric layer. The diffusion region and the metallic film constitute a capacitor bottom plate.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

An anti-fuse memory cell includes a substrate, a gate dielectric layer over the substrate, a word line gate over the gate dielectric layer, a first implant region on a first side of the word line gate, a bit line contact plug over the first implant region, a second implant region on a second side of the word line gate opposite the first side of the word line gate, an oxidized region on the second implant region and having a convex upper surface and a source line gate over the convex upper surface of the oxidized region.