In a customizable circuit an interconnect matrix is provided that includes only two conductive layers, the matrix defining a first layer of L-shaped conductive lines and a second layer of substantially L-shaped conductive line segments that are connected to electrical components.

A semiconductor device with an identification structure is provided. The semiconductor device includes a substrate and a metallization structure over the substrate. The metallization structure includes an interconnection region having a plurality of metal layers and an identification region isolated from the interconnection region. The identification region has an identification structure leveled with one of the metal layer. The identification structure includes at least one exposing recess and at least one exposing fuse. A method for manufacturing a semiconductor device with an identification structure and a method for tracing a production information of a semiconductor device are also provided.

An integrated circuit includes a polysilicon resistor having a plurality of segments, including first, second and third segments, the second segment located between and running about parallel to the first and third segments. A first header connects the first and second segments, and a second header connects the second and third segments. A first metal silicide layer located over the first header extends over the first and second segments toward the second header. A second metal silicide layer located over the second header extends over the second and third segments toward the first header. A dielectric layer is located over and contacts the first, second and third segments between the first and second metal silicide layers.

For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

An integrated circuit includes a polysilicon resistor having a plurality of segments, including first, second and third segments, the second segment located between and running about parallel to the first and third segments. A first header connects the first and second segments, and a second header connects the second and third segments. A first metal silicide layer located over the first header extends over the first and second segments toward the second header. A second metal silicide layer located over the second header extends over the second and third segments toward the first header. A dielectric layer is located over and contacts the first, second and third segments between the first and second metal silicide layers.

For simplifying the dual-damascene formation steps of a multilevel Cu interconnect, a formation step of an antireflective film below a photoresist film is omitted. Described specifically, an interlayer insulating film is dry etched with a photoresist film formed thereover as a mask, and interconnect trenches are formed by terminating etching at the surface of a stopper film formed in the interlayer insulating film. The stopper film is made of an SiCN film having a low optical reflectance, thereby causing it to serve as an antireflective film when the photoresist film is exposed.

A semiconductor integrated circuit device includes a fuse element that can be laser trimmed to adjust the characteristics of the semiconductor integrated circuit device, The semiconductor integrated circuit device includes an interlayer insulating film above the fuse element, and the thickness of the interlayer insulating film is reduced by using an amorphous silicon layer that is formed by sputtering as a material of the fuse element, and by forming the amorphous silicon layer at the same time as metal wiring is formed. The laser trimming processing is thus stabilized without needing a high level of dry etching stabilization control.

A semiconductor structure and a method for forming the semiconductor structure are disclosed. The method includes receiving a first integrated circuit component having a seal ring and a fuse structure, wherein the fuse structure is electrically connected to a ground through the seal ring; receiving a second integrated circuit component having a first capacitor; bonding the second integrated circuit component to the first integrated circuit component; electrically connecting the first capacitor to the fuse structure, wherein the first capacitor is electrically connected to the ground through the fuse structure; and blowing the fuse structure after a treatment.

A fuse element includes a metal layer disposed on a substrate. The metal layer includes an intermediate segment, a first block and a second block. The first block and the second block are electrically connected to two respective ends of the intermediate segment. The fuse element also includes a dielectric layer covering the intermediate segment, the first block and the second block, a first passivation layer disposed on the dielectric layer, and a second passivation layer disposed on the first passivation layer. The fuse element further includes an opening penetrating through the first passivation layer, the second passivation layer and a portion of the dielectric layer, and located above the intermediate segment. In addition, a protective film is disposed on a bottom and a portion of a sidewall of the opening, and covers the first passivation layer exposed by the opening.

A semiconductor structure and a method for forming the semiconductor structure are disclosed. The method includes the following operations. A first integrated circuit component having a fuse structure is received. A second integrated circuit component having an inductor is received. The second integrated circuit component is bonded to the first integrated circuit component. The inductor is electrically connected to the fuse structure, wherein the inductor is electrically connected to a ground through the fuse structure.