A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers. The electrically conductive layers include an intermetallic alloy of aluminum and at least one metal other than aluminum. Memory openings vertically extend through the alternating stack. Memory opening fill structures are located in a respective one of the memory openings and include a respective vertical semiconductor channel and a respective vertical stack of memory elements.

A cavity may be formed in a dielectric material layer overlying a substrate. A layer stack including a metallic barrier liner, a metallic fill material layer, and a metallic capping material may be deposited in the cavity and over the dielectric material layer. Portions of the layer stack located above a horizontal plane including a top surface of the dielectric material layer may be removed. A contiguous set of remaining material portions of the layer stack includes a metal interconnect structure that is free of a pitted surface.

An interconnection structure includes a first dielectric layer, a first conductive feature, a first liner layer, a second conductive feature, a second liner layer, and an air gap. The first conductive feature is disposed in the first dielectric layer. The first liner layer is disposed between the first conductive feature and the first dielectric layer. The second conductive feature penetrates the first dielectric layer. The second liner layer is disposed between the second conductive feature and the first dielectric layer. The air gap is disposed in the first dielectric layer between the first liner layer and the second liner layer. The first liner layer and the second liner layer include metal oxide, metal nitride, or silicon oxide doped carbide.

Contacting a multiplicity of seed crystals with an amorphous metallic alloy layer to form an amorphous precursor film or depositing an amorphous precursor film on a substrate and annealing the amorphous precursor film at a temperature between 50° C. and 400° C. to yield the metallic film with grains separated by grain boundaries.

A semiconductor device includes a semiconductor substrate, a field-effect transistor arranged at least partially on the semiconductor substrate and used in an analog circuit, and having a P-type gate electrode, an interlayer insulating film arranged on the field-effect transistor, and a hydrogen shielding metal or metallic film arranged on the interlayer insulting film and covering the P-type gate electrode and configured to shield hydrogen.

A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

Integrated circuit structures including an interconnect feature without a higher-resistance liner material. In absence of a liner, metal of low resistance directly contacts an adjacent dielectric material, enabling lower resistance interconnect. Even for low-k dielectric compositions, adhesion of the metal to the dielectric material is improved through the incorporation of nitrogen proximal to the interface. Prior to deposition of the metal upon a surface of the dielectric, the surface is exposed to nitrogen species to form a nitrogen-rich compound at the surface. The metal deposited upon the surface may then be nitrogen-lean, for example a substantially pure elemental metal or metal alloy.

To provide a wiring material which does not require a diffusion barrier layer and exhibits excellent conductivity and adhesion property between a conductor and an insulator and a semiconductor element using the same. The wiring structure of the present invention includes a conductor containing an intermetallic compound and an insulator layer. The intermetallic compound preferably contains two or more kinds of metal elements selected from the group consisting of Al, Fe, Co, Ni, and Zn. In addition, the intermetallic compound is preferably one or more kinds selected from an intermetallic compound containing Al and Co, an intermetallic compound containing Al and Fe, an intermetallic compound containing Al and Ni, an intermetallic compound containing Co and Fe, or an intermetallic compound containing Ni and Zn.

A first conductor pattern is formed on a semiconductor substrate of a scribing region via an insulating film. A plurality of second conductor patterns connected to the first conductor pattern are formed on the first conductor pattern. A third conductor pattern connected to the plurality of second conductor patterns is formed on the plurality of second conductor pattern. The scribing region is cut off in a Y direction by using a dicing blade so that a part of the scribing region is left in a chip region. In an X direction, a width of the dicing blade is narrower than each width of the first and second conductor patterns. After cutting off the scribing region, a part of the first conductor pattern, all or a part of at least one of the plurality of second conductor patterns, and a part of the third conductor pattern are left in the scribing region.

A semiconductor device includes a lower structure including a substrate and a cell structure on the substrate and a plurality of interconnection layers, which are stacked on the lower structure in a first direction extending perpendicular to a top surface of the substrate. An uppermost interconnection layer of the plurality of interconnection layers includes uppermost conductive lines. Each of the uppermost conductive lines includes a lower metal compound pattern, a metal pattern, an upper metal compound pattern, and a capping pattern, which are sequentially stacked in the first direction. The lower metal compound pattern, the metal pattern, and the upper metal compound pattern include a same metallic element.