Provided are an interconnect structure and an electronic device including the same. The interconnect structure may include a conductive wiring having a certain pattern, a dielectric layer on side surfaces of the conductive wiring, a capping layer on the conductive wiring, and a graphene layer on the dielectric layer. The graphene layer may include a graphene material. A ratio of carbons having sp.sup.3 bonds to carbons having sp.sup.2 bonds in the graphene material is 1 or less.

A semiconductor device includes a gate structure on a semiconductor fin, a dielectric layer on the gate structure, and a gate contact extending through the dielectric layer to the gate structure. The gate contact includes a first conductive material on the gate structure, a top surface of the first conductive material extending between sidewalls of the dielectric layer, and a second conductive material on the top surface of the first conductive material.

The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.

The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.

A method for fabricating an advanced metal conductor structure is described. A pattern in a dielectric layer is provided. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is created over the patterned dielectric. A ruthenium layer is deposited over the adhesion promoting layer. Using a physical vapor deposition process, a cobalt layer is deposited over the ruthenium layer. A thermal anneal is performed which reflows the cobalt layer to fill the set of features to form a set of metal conductor structures. In another aspect of the invention, an integrated circuit device is formed using the method.

An Ag alloy film used for a reflecting electrode or an interconnection electrode, the Ag alloy film exhibiting low electrical resistivity and high reflectivity and having exceptional oxidation resistance under cleaning treatments such as an O.sub.2 plasma treatment or UV irradiation, wherein the Ag alloy film contains either In in an amount of larger than 2.0 atomic % to 2.7 atomic % or smaller; or Zn in an amount of larger than 2.0 atomic % to 3.5 atomic % or smaller; or both. The Ag alloy film may further contain Bi in an amount of 0.01 to 1.0 atomic %.

The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes forming a liner-free conductive structure on a cobalt conductive structure disposed on a substrate, depositing a cobalt layer on the liner-free conductive structure and exposing the liner-free conductive structure to a heat treatment. The method further includes removing the cobalt layer from the liner-free conductive structure.

Integrated circuit devices and methods of forming the same are provided. The methods may include providing an underlying structure including a first insulating layer and forming a first metal structure, a first adhesion pattern, and a second insulating layer thereon. The second insulating layer may be on a side surface of the first metal structure, the first metal structure may include a metal pattern and a second adhesion pattern between the first insulating layer and the metal pattern, and the first adhesion pattern contacts side surfaces of the metal pattern and the second adhesion pattern. The methods may also include forming a second metal structure on the first metal structure. The metal pattern may include a contact portion protruding upwardly beyond an upper surface of the second insulating layer or may include an upper surface recessed with respect to the upper surface of the second insulating layer.

An electronic device is disclosed. In an embodiment an electronic device includes at least one first carrier and at least one semiconductor chip, wherein the first carrier has a cavity in which the semiconductor chip is arranged.

There is provided a semiconductor device including a first conductive layer formed on a substrate; a second conductive layer serving as a wiring layer and a barrier layer provided between the first conductive layer and the second conductive layer, wherein the barrier layer is made of a graphene film, and the second conductive layer includes a metal silicide compound, the metal silicide compound being provided so as to be in contact with the graphene film constituting the barrier layer.