A vertical semiconductor device includes insulation patterns, channel structures, a first metal pattern structure and a second metal pattern. The insulation patterns are spaced apart from each other in a vertical direction. Each insulation pattern extends in a first direction parallel to the upper surface of a substrate. The channel structures pass through the insulation patterns. The first metal pattern structure include at least one first metal material, and extend in the first direction. The first metal pattern structure are positioned in a gap between adjacent insulation patterns in the vertical direction, and the first metal pattern structure is at a central portion of the gap. The second metal pattern includes a metal material that is different from the at least one first metal material, the second metal pattern may be on opposite sidewalls of the first metal pattern structure to fill a remainder portion of the gap.

An integrated circuit includes a substrate, a transistor over the substrate, a first inter-metal dielectric (IMD) layer over the transistor, a metal via in the first IMD layer, a first 2-D material layer cupping an underside of the metal via, a second IMD layer over the metal via, a metal line in the second IMD layer, and a second 2-D material layer cupping an underside of the metal line. The second 2-D material layer span across the metal via and the first 2-D material layer.

A interconnect structure includes a lower metal, a dielectric layer, an upper metal, and a graphene layer. The dielectric layer laterally surrounds the lower metal. The upper metal is over the lower metal. The graphene layer is over a top surface of the upper metal and opposite side surfaces of the upper metal from a cross-sectional view.

A barrier layer is formed in a portion of a thickness of sidewalls in a recess prior to formation of an interconnect structure in the recess. The barrier layer is formed in the portion of the thickness of the sidewalls by a plasma-based deposition operation, in which a precursor reacts with a silicon-rich surface to form the barrier layer. The barrier layer is formed in the portion of the thickness of the sidewalls in that the precursor consumes a portion of the silicon-rich surface of the sidewalls as a result of the plasma treatment. This enables the barrier layer to be formed in a manner in which the cross-sectional width reduction in the recess from the barrier layer is minimized while enabling the barrier layer to be used to promote adhesion in the recess.

The present disclosure provides a method of forming an interconnect structure. The method includes forming a metal layer over a substrate, the metal layer including a first metal; forming a capping layer on the metal layer; patterning the capping layer and the metal layer, thereby forming trenches in the metal layer; depositing a first dielectric layer in the trenches; removing the capping layer, resulting in the first dielectric layer protruding from a top surface of the metal layer; depositing a second dielectric layer over the first dielectric layer and the metal layer; forming an opening in the second dielectric layer, thereby partially exposing the top surface of the metal layer; and forming a conductive feature in the opening and in electrical coupling with the metal layer, the conductive feature including a second metal.

Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.

An interconnect structure of a semiconductor device includes a conductive via and a barrier layer lining an interface between a dielectric layer and the conductive via. The barrier layer is selectively deposited along sidewalls of a recess formed in a dielectric layer. The conductive via is formed by selectively electroplating electrically conductive material such as rhodium, iridium, or platinum in an opening of the recess, where the conductive via is grown upwards from an exposed metal surface at a bottom of the recess. The conductive via includes an electrically conductive material having a low electron mean free path, low electrical resistivity, and high melting point. The interconnect structure of the semiconductor device has reduced via resistance and improved resistance to electromigration and/or stress migration.

A device includes a substrate, a dielectric layer over the substrate, and a conductive interconnect in the dielectric layer. The conductive interconnect includes a barrier/adhesion layer and a conductive layer over the barrier/adhesion layer. The barrier/adhesion layer includes a material having a chemical formula MX.sub.n, with M being a transition metal element, X being a chalcogen element, and n being between 0.5 and 2.

Provided are an interconnect structure and an electronic device including the same. The interconnect structure may include a conductive wiring having a certain pattern, a dielectric layer on side surfaces of the conductive wiring, a capping layer on the conductive wiring, and a graphene layer on the dielectric layer. The graphene layer may include a graphene material. A ratio of carbons having sp.sup.3 bonds to carbons having sp.sup.2 bonds in the graphene material is 1 or less.

A semiconductor structure includes a metal gate structure disposed over a semiconductor substrate, an interlayer dielectric (ILD) layer disposed over the metal gate structure, and a gate contact disposed in the ILD layer and over the metal gate structure, where a bottom surface of the gate contact is defined by a barrier layer disposed over the metal gate structure, where sidewall surfaces of the gate contact are defined by and directly in contact with the ILD layer, and where the barrier layer is free of nitrogen.