Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure may include a dielectric layer including a trench; a conductive line in the trench; and a first cap layer on an upper surface of the conductive line. The first cap layer may include a graphene-metal composite including graphene and a metal mixed with each other.

An interconnection structure, along with methods of forming such, are described. The structure includes a dielectric layer, a first conductive feature disposed in the dielectric layer, and a conductive layer disposed over the dielectric layer. The conductive layer includes a first portion and a second portion adjacent the first portion, and the second portion of the conductive layer is disposed over the first conductive feature. The structure further includes a first barrier layer in contact with the first portion of the conductive layer, a second barrier layer in contact with the second portion of the conductive layer, and a support layer in contact with the first and second barrier layers. An air gap is located between the first and second barrier layers, and the dielectric layer and the support layer are exposed to the air gap.

A metal structure includes a patterned molybdenum tantalum oxide layer and a patterned metal layer. The patterned molybdenum tantalum oxide layer is disposed on a first substrate, in which the patterned molybdenum tantalum oxide layer includes about 2 to 12 atomic percent of tantalum. Both of an atomic percent of molybdenum and an atomic percent of oxygen of the patterned molybdenum tantalum oxide layer are greater than the atomic percent of tantalum of the patterned molybdenum tantalum oxide layer. The patterned metal layer is disposed on the patterned molybdenum tantalum oxide layer.

An integrated circuit (IC) with a semiconductor device and an interconnect structure with carbon layers and methods of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a source/drain region on the fin structure, forming a contact structure on the S/D region, forming an oxide layer on the contact structure, forming a conductive carbon line within a first insulating carbon layer on the oxide layer, forming a second insulating carbon layer on the first insulating carbon layer, and forming a via within the second insulating carbon layer.

A method includes forming one or more vias in a first layer, forming one or more vias in at least a second layer different than the first layer, aligning at least a first via in the first layer with at least a second via in the second layer, and bonding the first layer to the second layer by filling the first via and the second via with solder material using injection molded soldering.

A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A first conductive via is formed, extending from a first surface of the substrate, where the first surface is opposite the second redistribution structure, the first conductive via contacting a first conductive element in the second redistribution structure. Forming the first conductive via includes patterning an opening in the substrate, extending the opening to expose the first conductive element, where extending the opening includes using a portion of a second conductive element in the first redistribution structure as an etch mask, and filling the opening with a conductive material.

Middle-of-line (MOL) interconnects that facilitate reduced capacitance and/or resistance and corresponding techniques for forming the MOL interconnects are disclosed herein. An exemplary MOL interconnect structure includes a device-level contact disposed in a first insulator layer and a ruthenium structure disposed in a second insulator layer disposed over the first insulator layer. The device-level contact physically contacts an integrated circuit feature, and the ruthenium structure physically contacts the device-level contact. An air gap separates sidewalls of the ruthenium structure from the second insulator layer. A top surface of the ruthenium structure is lower than a top surface of the second insulator layer. A via disposed in a third insulator layer extends below the top surface of the second insulator layer to physically contact the ruthenium structure. A remainder of a dummy contact spacer layer may separate the first insulator layer and the second insulator layer.

A method for manufacturing a semiconductor device includes forming a trench in at least one dielectric layer; and forming an interconnect structure in the trench, wherein forming the interconnect structure includes forming a first conductive layer on a bottom surface of the trench, and partially filling the trench, and forming a second conductive layer on the first conductive layer, and filling a remaining portion of the trench, wherein the second conductive layer comprises a different material from the first conductive layer, and wherein an amount of the first conductive layer in the trench is controlled so that an aspect ratio of the second conductive layer has a value that is determined to result in columnar grain boundaries in the second conductive layer.

A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes a core material surrounded by a jacket material, wherein the jacket material exhibits a first resistivity ρ1 and the core material exhibits a second resistivity ρ2 and ρ2 is less than ρ1.

Provided is a semiconductor device including electronic components electrically joined to each other via a metal nanoparticle sintered layer, wherein the metal nanoparticle sintered layer has formed therein a metal diffusion region in which a metal constituting a metallization layer formed on a surface of one of the electronic components is diffused, and in which the metal is present in an amount of 10 mass % or more and less than 100 mass % according to TEM-EDS analysis, and wherein the metal diffusion region has a thickness smaller than a thickness of the metallization layer.