A low resistance metal is charged into holes formed in a semiconductor substrate to thereby form through electrodes. Post electrodes of a wiring-added post electrode component connected together by a support portion thereof are simultaneously fixed to and electrically connected to connection regions formed on an LSI chip. On the front face side, after resin sealing, the support portion is separated so as to expose front face wiring traces. On the back face side, the semiconductor substrate is grounded so as to expose tip ends of the through electrodes. The front face wiring traces exposed to the front face side and the tip ends of the through electrodes exposed to the back face side are used as wiring for external connection.

A packaged semiconductor system, including: at least one electronic device on a device mounting surface of a substrate having terminals for attaching bond wires; at least one discrete component adjacent to the at least one electronic device, a second electrode of the at least one discrete component parallel to and spaced from a first electrode by a component body; the first electrode a metal foil having a protrusion extending laterally from the body and having a surface facing towards the second electrode; bonding wires interconnecting respective terminals of the at least one electronic device, the first electrode and the second electrode, and bonded to the surface of the second electrode and to the protrusion that extend away from the respective surfaces in a same direction; and packaging compound covering portions of the at least one electronic device, the at least one discrete component, and the bonding wires.

A device includes a non-insulator structure, a first dielectric layer, and a first conductive feature. The first dielectric layer is over the non-insulator structure. The first conductive feature is in the first dielectric layer and includes carbon nano-tubes. The first catalyst layer is between the first conductive feature and the non-insulator structure. A top of the first catalyst layer is lower than a top of the first conductive feature.

A semiconductor device includes an interconnect substrate, an interconnect trace disposed on an upper surface of the interconnect substrate, a semiconductor chip mounted on the upper surface of the interconnect substrate, an adhesive resin layer disposed between the upper surface of the interconnect substrate and a lower surface of the semiconductor chip to bond the interconnect substrate and the semiconductor chip, the adhesive resin layer including an opening at a bottom of which an upper surface of the interconnect trace is situated, a barrier layer covering a sidewall of the opening, and conductive paste disposed inside the opening, wherein an electrode terminal of the semiconductor chip situated at the lower surface thereof is disposed inside the opening, with the conductive paste filling a space between the barrier layer and the electrode terminal.

A semiconductor device and a method of manufacturing the same, the device including a through-hole electrode structure extending through a substrate; a redistribution layer on the through-hole electrode structure; and a conductive pad, the conductive pad including a penetrating portion extending through the redistribution layer; and a protrusion portion on the penetrating portion, the protrusion portion protruding from an upper surface of the redistribution layer, wherein a central region of an upper surface of the protrusion portion is flat and not closer to the substrate than an edge region of the upper surface of the protrusion portion.

A packaged semiconductor system, including: at least one electronic device on a device mounting surface of a substrate having terminals for attaching bond wires; at least one discrete component adjacent to the at least one electronic device, a second electrode of the at least one discrete component parallel to and spaced from a first electrode by a component body; the first electrode a metal foil having a protrusion extending laterally from the body and having a surface facing towards the second electrode; bonding wires interconnecting respective terminals of the at least one electronic device, the first electrode and the second electrode, and bonded to the surface of the second electrode and to the protrusion that extend away from the respective surfaces in a same direction; and packaging compound covering portions of the at least one electronic device, the at least one discrete component, and the bonding wires.

A coating can be provided on a substrate. Fabrication of the coating can include forming a solid layer in a specified region of the substrate while supporting the substrate in a coating system using a gas cushion. For example, a liquid coating can be printed over the specified region while the substrate is supported by the gas cushion. The substrate can be held for a specified duration after the printing the patterned liquid. The substrate can be conveyed to a treatment zone while supported using the gas cushion. The liquid coating can be treated to provide the solid layer including continuing to support the substrate using the gas cushion.

An apparatus for manufacturing a thermoelectric module is provided. The thermoelectric module includes thermoelectric pellets, first electrodes, second electrodes, and an insulating substrate. The apparatus includes a fixing tray to which the thermoelectric module is fixed, a first die including a first heating member configured to heat a first adhesive layer, which is interposed between the thermoelectric pellets and the first electrodes. The fixing tray is mounted on the first die such that the insulating substrate faces the first heating member. A second die includes a second heating member configured to heat a second adhesive layer, which is interposed between the thermoelectric pellets and the second electrodes, the second die facing the second electrodes. A transfer unit is configured to transfer at least one of the first die and the second die to adjust a distance between the first die and the second die.

A method of forming a material layer on a substrate comprises loading a substrate into a printing zone of a coating system using a substrate handler, printing an organic ink material on a substrate while the substrate is located in the printing zone, transferring the substrate from the printing zone to a treatment zone of the coating system, treating the organic ink material deposited on the substrate in the treatment zone to form a film layer on the substrate, and removing the substrate from the treatment zone using the substrate handler.

A semiconductor device includes a non-insulator structure, at least one carbon nano-tube (CNT), a dielectric layer, and a graphene-based conductive layer. The CNT is over the non-insulator structure. The dielectric layer surrounds the CNT. The graphene-based conductive layer is over the at least one CNT. The CNTs and the graphene-based conductive layer have low resistance.