A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure comprises at least one two-dimensional (2D) conductive structure; a dielectric layer disposed on the 2D conductive structure; and at least one interconnect structure disposed in the dielectric layer and extending into the 2D conductive structure, wherein the interconnect structure laterally connects to at least one edge of the 2D conductive structure.

Exemplary semiconductor processing methods may include providing a carbon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be disposed within the processing region of the semiconductor processing chamber. The substrate may include a low dielectric constant material defining one or more features, a liner extending across the low dielectric constant material and within the one or more features, and a metal-containing layer deposited on the liner and extending within the one or more features. The methods may include forming a layer of material on at least a portion of the liner and the metal-containing layer. The layer of material may include graphene. The methods may include removing substantially all of the portion of the layer of material on the liner.

Interconnects may comprise a sandwich-structured composite comprising a core layer located between two thermosetting polymer layers. The core layer may comprise 80 wt % to 95 wt % conductive metal and a polymer. The conductive metal may comprise silver (Ag). The polymer may comprise polydimethylsiloxane (PDMS). Interconnects may be particularly suited for use in electronic devices, such as a flexible batteries and wearable electronic devices.

Metallization interconnect structures, integrated circuit devices, and methods related to high aspect ratio interconnects are discussed. A self assembled monolayer is selectively formed on interlayer dielectric sidewalls of an opening that exposes an underlying metallization structure. A first metal is formed on the underlying metallization structure and within only a bottom portion of the self assembled monolayer. The exposed portion of the self assembled monolayer is removed and a second metal is formed over the first metal.

The present application discloses a semiconductor device with a landing pad of conductive polymer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a dielectric layer disposed over the substrate, a plug disposed in the dielectric layer, and a landing pad of conductive polymer disposed over the dielectric layer. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a conductive polymer layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer in a self-aligned manner. The landing pad of conductive polymer comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion.

A device includes a non-insulator structure, a first dielectric layer, and a first conductive feature. The first dielectric layer is over the non-insulator structure. The first conductive feature is in the first dielectric layer and includes carbon nano-tubes. The first catalyst layer is between the first conductive feature and the non-insulator structure. A top of the first catalyst layer is lower than a top of the first conductive feature.

A method of forming a material layer on a substrate comprises loading a substrate into a printing zone of a coating system using a substrate handler, printing an organic ink material on a substrate while the substrate is located in the printing zone, transferring the substrate from the printing zone to a treatment zone of the coating system, treating the organic ink material deposited on the substrate in the treatment zone to form a film layer on the substrate, and removing the substrate from the treatment zone using the substrate handler.

A power module (10) includes a power semiconductor chip (1) and a Cu circuit (3) having the power semiconductor chip (1) provided on one surface. The power module (10) includes: a sintering layer (2) joining the power semiconductor chip (1) and the Cu circuit (3) by using a sintering paste; and a heat dissipation sheet (4) provided for joining a Cu base plate (5) to the other surface of the Cu circuit (3), in which in a first laminated structure in which the power semiconductor chip (1), the sintering layer (2), the Cu circuit (3), and the heat dissipation sheet (4) are laminated, the total thermal resistance XA in the direction of lamination is equal to or less than 0.30 (K/W).

The present application discloses a semiconductor device with a landing pad of conductive polymer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a dielectric layer disposed over the substrate, a plug disposed in the dielectric layer, and a landing pad of conductive polymer disposed over the dielectric layer. The method includes: providing a substrate; forming a dielectric layer with a plug over the substrate; performing an etching process to remove a portion of the dielectric layer to expose a protruding portion of the plug; forming a conductive polymer layer covering the dielectric layer and the protruding portion; and performing a thermal process to form a landing pad over the dielectric layer in a self-aligned manner. The landing pad of conductive polymer comprises a protruding portion of the plug, a first silicide layer disposed over the protruding portion, and a second silicide layer disposed on a sidewall of the protruding portion.

A packaged semiconductor system, including: at least one electronic device on a device mounting surface of a substrate having terminals for attaching bond wires; at least one discrete component adjacent to the at least one electronic device, a second electrode of the at least one discrete component parallel to and spaced from a first electrode by a component body; the first electrode a metal foil having a protrusion extending laterally from the body and having a surface facing towards the second electrode; bonding wires interconnecting respective terminals of the at least one electronic device, the first electrode and the second electrode, and bonded to the surface of the second electrode and to the protrusion that extend away from the respective surfaces in a same direction; and packaging compound covering portions of the at least one electronic device, the at least one discrete component, and the bonding wires.