A transient electronic device utilizes a glass-based interposer that is treated using ion-exchange processing to increase its fragility, and includes a trigger device operably mounted on a surface thereof. An integrated circuit (IC) die is then bonded to the interposer, and the interposer is mounted to a package structure where it serves, under normal operating conditions, to operably connect the IC die to the package I/O pins/balls. During a transient event (e.g., when unauthorized tampering is detected), a trigger signal is transmitted to the trigger device, causing the trigger device to generate an initial fracture force that is applied onto the glass-based interposer substrate. The interposer is configured such that the initial fracture force propagates through the glass-based interposer substrate with sufficient energy to both entirely powderize the interposer, and to transfer to the IC die, whereby the IC die also powderizes (i.e., visually disappears).

An integrated circuit includes a first domain supplied with power at a first supply voltage. A first transistor comprising in the first domain includes a first gate region and a first gate dielectric region. A second domain is supply with power at a second supply voltage and includes a second transistor having a second gate region and a second gate dielectric region, the second gate region being biased at a voltage that is higher than the first supply voltage. The first and second gate dielectric regions have the same composition, wherein that composition configures the first transistor in a permanently turned off condition in response to a gate bias voltage lower than or equal to the first supply voltage. The second transistor is a floating gate memory cell transistor, with the second gate dielectric region located between the floating and control gates.

A method of fabricating ultra-thin semiconductor devices includes forming an array of semiconductor dielets mechanically suspended on a frame with at least one tether connecting each semiconductor dielet of the array of semiconductor dielets to the frame.

An improved system and method for reading an upconversion response from nanoparticle inks is provided. A is adapted to direct a near-infrared excitation wavelength at a readable indicia, resulting in a near-infrared emission wavelength created by the upconverting nanoparticle inks. A short pass filter may filter the near-infrared excitation wavelength. A camera is in operable communication with the short pass filter and receives the near-infrared emission wavelength of the readable indicia. The system may further include an integrated circuit adapted to receive the near-infrared emission wavelength from the camera and generate a corresponding signal. A readable application may be in operable communication with the integrated circuit. The readable application receives the corresponding signal, manipulates the signal, decodes the signal into an output, and displays and/or stores the output.

The disclosure provides an integrated circuit (IC) structure with fluorescent materials, and related methods. An IC structure according to the disclosure may include a layer of fluorescent material on an IC component. The layer of fluorescent material defines a portion of an identification marker for the IC structure.

A PUF-film includes a circuit structure having a plurality of circuit elements, wherein the circuit structure is evaluable with respect to a plurality of electric capacitance values being arranged between the plurality of circuit elements, and is evaluable with respect to a plurality of electric resistance values of the plurality of circuit components.

A tamper-resistant memory is formed by placing a solid-state memory array between metal wiring layers in the upper portion of an integrated circuit (back-end of the line). The metal layers form a mesh that surrounds the memory array to protect it from picosecond imaging circuit analysis, side channel attacks, and delayering with electrical measurement. Interconnections between a memory cell and its measurement circuit are designed to protect each layer below, i.e., an interconnecting metal portion in a particular metal layer is no smaller than the interconnecting metal portion in the next lower layer. The measurement circuits are shrouded by the metal mesh. The substrate, metal layers and memory array are part of a single monolithic structure. In an embodiment adapted for a chip identification protocol, the memory array contains a physical unclonable function identifier that uniquely identifies the tamper-resistant integrated circuit, a symmetric encryption key and a release key.

A semiconductor device comprises a plurality of resistive memory element structures, at least a subset of the plurality of resistive memory element structures being associated with random analog resistive states. The random analog resistive states of the subset of the plurality of resistive memory element structures provide a unique identification of the semiconductor device.

A laminate carrier-like module lid including multiple laminate layers of non-conductive materials stacked one atop another, sensor circuitry embedded within the laminate carrier-like module lid, the sensor circuitry providing a continuous electrical circuit surrounding the electronic components of the multi-chip module package, and thermal circuitry embedded within the laminate carrier-like module lid, the thermal circuitry comprising solid copper traces to thermally conduct heat from the electronic components of the multi-chip module package.

A system is disclosed that includes an electronic package. The electronic package includes a package base couplable to a host substrate, and a package lid mechanically coupled to the package base that includes one or more transparent lid areas, configured to permit transmission of light. The electronic package further includes a thermal spreader bonded on a first side to a first side of the package lid. The thermal spreader includes one or more transparent spreader areas that are configured to allow transmission of light through the thermal spreader. The electronic package further includes one or more integrated circuits bonded to a second side of the thermal spreader that communicatively coupled to the host substrate. The electronic package further includes one or more optical paths that include at least one of the one or more transparent spreader areas configured adjacent to at least one of the transparent lid areas.