A display panel is provided. The display panel includes a plurality of signal lines and a testing circuit. The testing circuit includes a plurality of transistors electrically connected to the plurality of signal lines. The plurality of transistors are disposed in at least two groups, and a number of transistors of each group of the at least two groups is less than a total number of the plurality of signal lines. Therefore, the testing circuit of the display panel of the disclosure can reduce the circuit placement space in the horizontal direction.

Disclosed herein are a stretchable display panel and a stretchable device. The stretchable display panel comprises: a lower substrate having an active area and a non-active area surrounding the active area; a plurality of individual substrates disposed on the lower substrate, spaced apart from each other and located in the active area; a connection line electrically connecting a pad disposed on the individual substrate; a plurality of pixels disposed on the plurality of individual substrates; and an upper substrate disposed above the plurality of pixels, wherein the modulus of elasticity of the individual substrates is higher than that of at least one part of the lower substrate. Accordingly, the stretchable display device according to the present disclosure may have a structure that enables the stretchable display device to be more easily deformed when a user stretches or bends the stretchable display device and that can minimize damage to the components of the stretchable display device when the stretchable display device is deformed.

A semiconductor package may include an image sensor chip, a transparent substrate spaced apart from the image sensor chip, a joining structure in contact with a top surface of the image sensor chip and a bottom surface of the transparent substrate, on an edge region of the top surface of the image sensor chip, and a circuit substrate electrically connected to the image sensor chip. The image sensor chip may include a penetration electrode which penetrates at least a portion of an internal portion of the image sensor chip, and a terminal pad, which is on the edge region of the top surface of the image sensor chip and is connected to the penetration electrode. The joining structure may include a spacer and an adhesive layer which is between and attached to the spacer and the image sensor chip. The joining structure may the terminal pad.

A semiconductor package may include an image sensor chip, a transparent substrate spaced apart from the image sensor chip, a joining structure in contact with a top surface of the image sensor chip and a bottom surface of the transparent substrate, on an edge region of the top surface of the image sensor chip, and a circuit substrate electrically connected to the image sensor chip. The image sensor chip may include a penetration electrode which penetrates at least a portion of an internal portion of the image sensor chip, and a terminal pad, which is on the edge region of the top surface of the image sensor chip and is connected to the penetration electrode. The joining structure may include a spacer and an adhesive layer which is between and attached to the spacer and the image sensor chip. The joining structure may the terminal pad.

A battery system has a battery cell including a can, and a ceramic substrate, including a patterned metallized surface, mounted to the can via a thermally conductive adhesive. The battery system also has a monolithic integrated circuit that measures and transmits data about the cell mounted to the patterned metallized surface such that the ceramic substrate and monolithic integrated circuit are electrically isolated from one another.

A battery system has a battery cell including a can, and a ceramic substrate, including a patterned metallized surface, mounted to the can via a thermally conductive adhesive. The battery system also has a monolithic integrated circuit that measures and transmits data about the cell mounted to the patterned metallized surface such that the ceramic substrate and monolithic integrated circuit are electrically isolated from one another.

Integrated circuit (IC) chips and seal ring structures are provided. An IC chip according to the present disclosure includes an interconnect structure that includes a first metal line, a second metal line, a third metal line, a fourth metal line, and a fifth meal line extending along a first direction, a first group of lateral connectors disposed between the second metal line and the third metal line or between the fourth metal line and the fifth metal line, and a second group of lateral connectors disposed between the first metal line and the second metal line or between the third metal line and the fourth metal line.

A semiconductor chip, a semiconductor package including the same, and a method of fabricating the same, the semiconductor chip including a substrate that includes a device region and an edge region; a device layer and a wiring layer that are sequentially stacked on the substrate; a subsidiary pattern on the wiring layer on the edge region; a first capping layer that covers a sidewall of the subsidiary pattern, a top surface of the wiring layer, and a sidewall of the wiring layer, the first capping layer including an upper outer sidewall and a lower outer sidewall, the lower outer sidewall being offset from the upper outer sidewall; and a buried dielectric pattern in contact with the lower outer sidewall of the first capping layer and spaced apart from the upper outer sidewall of the first capping layer.

A method of forming an assembly is provided. The method includes attaching a packaged semiconductor device to a substrate. An isolation structure is formed and located between the packaged semiconductor device and the substrate. An underfill material is dispensed between the packaged semiconductor device and the substrate. The isolation structure prevents the underfill material from contacting a first conductive connection formed between the packaged semiconductor device and the substrate.

Chip sealing structures and methods of manufacture are described. In an embodiment, a chip structure includes a main body area formed of a substrate, a back-end-of-the-line (BEOL) build-up structure spanning over the substrate, and chip edge sidewalls extending from a back surface of the substrate to a top surface of the BEOL build-up structure and laterally surrounding the substrate and the BEOL build-up structure. In accordance with embodiments, the chip structure may further include a conformal sealing layer covering at least a first chip edge sidewall of the chip edge sidewalls and a portion of the top surface of the BEOL build-up structure, and forming a lip around the top surface of the BEOL build-up structure.