A semiconductor device includes: a semiconductor element; a support member; a bonding layer interposed between the semiconductor element and the support member; and a sealing resin that covers the semiconductor element and at least a portion of the support member, wherein the bonding layer is a layer in which a layer containing first metal and a layer containing second metal are integrated without going through a molten state, and wherein the support member includes a first surface facing in a thickness direction and facing a side on which the semiconductor element is located, and a plurality of first recesses located outside the bonding layer and recessed from the first surface when viewed along the thickness direction.

A semiconductor package includes a base substrate having a plurality of upper pads and a plurality of first and second lower pads, a semiconductor chip disposed on the base substrate and electrically connected to the plurality of upper pads, a solder resist layer having a plurality of openings exposing a region of each of the plurality of first and second lower pads, the exposed regions of the plurality of first and second lower pads having the same size, a plurality of first external connection conductors respectively disposed on the exposed regions of the plurality of first lower pads and having a first height and a first volume, and a plurality of second external connection conductors respectively disposed on the exposed regions of the plurality of second lower pads and having a second height, greater than the first height, and a second volume, greater than the first volume.

A distributed inductance integrated field effect transistor (FET) structure, comprising a plurality of FETs. Each FET comprises a plurality of source regions, a gate region having a plurality of gate fingers extending from a gate bus bar, a drain region having a plurality of drain finger extending from a drain bus bar between the plurality of gate fingers, wherein the gate region controls current flow in a conductive channel between the drain region and source region. A first distributed inductor connects the gate regions of adjacent ones of the plurality of FETs; and a second distributed inductor connects the drain regions of adjacent ones of the plurality of FETs.

A lead frame includes: a frame body; a plurality of leads individually projecting from the frame body; and a recess formed across one surfaces of the leads adjacent to each other with the frame body therebetween, the recess including a first recess, and a second recess partially overlapping the first recess in a bottom surface thereof and having a smaller depth than the first recess.

A semiconductor device includes: an interconnect substrate including a plurality of interconnect layers; a first semiconductor chip disposed over the interconnect substrate; a second semiconductor chip disposed over the first semiconductor chip in a shifted manner and including a plurality of metal bumps on a surface of the second semiconductor chip facing the interconnect substrate; and a plurality of columnar electrodes connecting the interconnect structure to the metal bumps.

Improving motion sensor robustness utilizing a room-temperature-volcanizing (RTV) material via a solder resist dam is presented herein. A sensor package comprises: a first semiconductor die; a second semiconductor die that is attached to the first semiconductor die to form a monolithic die; and a substrate comprising a top portion and a bottom portion, in which the top portion comprises a plurality of solder resist dams, the monolithic die is attached to the top portion of the substrate via the RTV material being disposed in a defined area of the top portion of the substrate, and the bottom portion of the substrate comprises electrical terminals that facilitate attachment and electrical coupling of signals of the sensor package to a printed circuit board.

A multi-chip module (MCM) package includes a leadframe including half-etched lead terminals including a full-thickness and half-etched portion, and second lead terminals including a thermal pad(s). A first die is attached by a dielectric die attach material to the half-etched lead terminals. The first die includes first bond pads coupled to first circuitry configured for receiving a control signal and for outputting a coded signal and a transmitter. The second die includes second bond pads coupled to second circuitry configured for a receiver with a gate driver. The second die is attached by a conductive die attach material to the thermal pad. Bond wires include die-to-die bond wires between a portion of the first and second bond pads. A high-voltage isolation device is between the transmitter and receiver. A mold compound encapsulates the first and the second die.

A semiconductor package includes: a package substrate, a first stack structure disposed on the package substrate, the first stack structure including first semiconductor chips stacked and connected to each other by bonding wires, a second stack structure disposed on the first stack structure, and including second semiconductor chips stacked, the second stack structure having an overhang region protruding beyond an uppermost first semiconductor chip of the first stack structure among the first semiconductor chips, an adhesive member covering a lower surface of the second stack structure and adhered to a portion of upper surfaces of the first stack structure, and an encapsulant disposed on the package substrate and covering the first stack structure and the second stack structure, wherein at least a portion of the bonding wires are buried in the die adhesive film in the overhang region to support the second stack structure.

In some examples, a package comprises a semiconductor die and a bond pad formed upon the semiconductor die. The bond pad has a protrusion on a top surface of the bond pad. The package also comprises a metal contact and a bond wire coupled to the protrusion and to the metal contact.

An electronic device includes: a substrate with obverse and reverse surfaces spaced apart in a thickness direction; an electronic element having an obverse surface formed with a first obverse surface electrode; a wiring portion on the substrate obverse surface and configured to transmit a control signal for the electronic element; a conduction member with obverse and reverse surfaces spaced apart in the thickness direction, where the reverse surface is joined to the wiring portion; a conductive first lead on the substrate obverse surface; and a first connecting member joined to the obverse surface of the conduction member and the first obverse surface electrode. The first lead includes a first pad portion spaced apart from the wiring portion and to which the electronic element is joined. The wiring portion and the first obverse surface electrode are electrically connected to each other via the conduction member and the first connecting member.