A method includes forming one or more vias in a first layer, forming one or more vias in at least a second layer different than the first layer, aligning at least a first via in the first layer with at least a second via in the second layer, and bonding the first layer to the second layer by filling the first via and the second via with solder material using injection molded soldering.

An electronic component includes a leadframe and a first semiconductor die. The leadframe includes a leadframe top side, a leadframe bottom side opposite the leadframe top side, and a top notch at the leadframe top side. The top notch includes a top notch base located between the leadframe top side and the leadframe bottom side, and defining a notch length of the top notch, and can also include a top notch first sidewall extended, along the notch length, from the leadframe top side to the top notch base. The first semiconductor die can include a die top side a die bottom side opposite the die top side and mounted onto the leadframe top side, and a die perimeter. The top notch can be located outside the die perimeter. Other examples and related methods are also disclosed herein.

An electronic device comprises a supporting substrate, a flexible substrate disposed on the supporting substrate, a plurality of electronic units and a conductive pattern layer. The flexible substrate is bent from a front side to a back side of the supporting substrate, and a portion of the flexible substrate is disposed on the back side of the supporting substrate. The electronic units are disposed within a display region of the flexible substrate. The conductive pattern layer extends from the display region to the portion of the flexible substrate, and the conductive pattern layer electrically connects at least two of the electronic units.

An object is to provide a technique capable of enhancing electrical characteristics and reliability of a semiconductor device. The semiconductor device includes a plurality of semiconductor chips, a plurality of electrodes each being electrically connected to each of the plurality of semiconductor chips, a sealing member, and a joint part. The sealing member covers the plurality of semiconductor chips, and parts being connected to the plurality of semiconductor chips, of the plurality of electrodes. The joint part is disposed outside the sealing member to electrically connect parts which are not covered by the sealing member, of the plurality of electrodes.

A memory unit having a plurality of memory chips comprises: the memory unit that has a plurality of memory chips that are stacked; and protruding terminals that are disposed protruding from a side surface along the stacking direction of the memory unit, wherein the protruding terminals have surfaces that are positioned in a direction orthogonal to the protrusion direction, and between said surfaces, the surface roughness of a surface facing one way is greater than the surface roughness of a surface facing the other way.

A header for a semiconductor package, includes an eyelet having a first surface, a second surface opposite to the first surface, a side surface, and a through hole penetrating the eyelet from the first surface to the second surface, a lead inserted through the through hole, and a metal base bonded to the second surface of the eyelet. The lead is bent at the second surface of the eyelet and protrudes from the side surface of the eyelet in a plan view. The metal base is spaced apart from the lead. The lead, located at a position overlapping the eyelet in the plan view, is disposed within a thickness range of the metal base in a side view.

A resin composition is disclosed that includes a thermosetting base resin; a curing agent; an inorganic filler; and at least one fluorine resin powder selected from polyvinylidene fluoride, polychlorotetrafluoroethylene, and a tetrafluoroethylene/perfluoro(alkyl vinyl ether)/chlorotrifluoroethylene copolymer, and a semiconductor device which is fabricated by being sealed using a sealant formed of the resin composition.

A method includes forming one or more vias in a substrate, forming a first photoresist layer on a top surface of the substrate and a second photoresist layer on a bottom surface of the substrate, patterning the first photoresist layer and the second photoresist layer to remove at least a first portion of the first photoresist layer and at least a second portion of the second photoresist layer, filling the one or more vias, the first portion and the second portion with solder material using injection molded soldering, and removing remaining portions of the first photoresist layer and the second photoresist layer.

An electronic device comprises a supporting substrate, a flexible substrate disposed on the supporting substrate, a plurality of electronic units and a conductive pattern layer. The flexible substrate is bent from a front side to a back side of the supporting substrate, and a portion of the flexible substrate is disposed on the back side of the supporting substrate. The electronic units are disposed within a display region of the flexible substrate. The conductive pattern layer extends from the display region to the portion of the flexible substrate, and the conductive pattern layer electrically connects at least two of the electronic units.

Some embodiments relate to a three-dimensional (3D) integrated circuit (IC). The 3D IC includes a first IC die comprising a first semiconductor substrate, and a first interconnect structure over the first semiconductor substrate. The 3D IC also includes a second IC die comprising a second semiconductor substrate, and a second interconnect structure that separates the second semiconductor substrate from the first interconnect structure. A seal ring structure separates the first interconnect structure from the second interconnect structure and perimetrically surrounds a gas reservoir between the first IC die and second IC die. The seal ring structure includes a sidewall gas-vent opening structure configured to allow gas to pass between the gas reservoir and an ambient environment surrounding the 3D IC.