A semiconductor device includes a substrate, a conductive part, a controller module and a sealing resin. The substrate has a substrate obverse surface and a substrate reverse surface facing away from each other in a z direction. The conductive part is made of an electrically conductive material on the substrate obverse surface. The controller module is disposed on the substrate obverse surface and electrically connected to the conductive part. The sealing resin covers the controller module and at least a portion of the substrate. The conductive part includes an overlapping wiring trace having an overlapping portion overlapping with the electronic component as viewed in the z direction. The overlapping portion of the overlapping wiring trace is not electrically bonded to the controller module.

A semiconductor device includes a pre-molded leadframe mounting substrate. The substrate includes a die pad (configured to have a semiconductor die mounted thereon) and a first electrically conductive pad and a second electrically conductive pad. A strip of insulating material is molded between the first and second electrically conductive pads to provide a mutually electrically insulation and extends in a longitudinal direction with the first electrically conductive pad and the second electrically conductive pad lying on opposite sides of the strip of insulating material. A semiconductor die is arranged on the die pad in register with the strip of insulating material. A single electrically conductive ribbon extending in register with the strip of insulating material electrically couples the semiconductor die with both the first and second electrically conductive pads to provide a common current flow path from the semiconductor die towards the first and the second electrically conductive pads.

A hybrid embedded packaging structure and a manufacturing method thereof are disclosed. The structure includes: a substrate with a first insulating layer, a conductive copper column, a chip-embedded cavity and a first circuit layer; a first electronic device arranged inside the chip-embedded cavity; a second electronic device arranged on a back surface of the first electronic device; a second insulating layer covering and filling the chip-embedded cavity and an upper layer of the substrate, exposing part of the first circuit layer and a back surface of part of the second electronic device or part of the first electronic device; a second circuit layer electrically connected with the conductive copper column and a terminal of the first electronic device; a conducting wire electrically connecting the first circuit layer with a terminal of the second electronic device; and a protection cover arranged on the top surface of the substrate.

A circuit module includes a substrate with a patterned metal surface. The patterned metal surface includes a conductive terminal pad, a first conductive pad, and a second conductive pad that is non-adjacent to the conductive terminal pad. A first circuit portion is assembled on the first conductive pad and a second circuit portion is assembled on the second conductive pad. A conductive bridge electrically couples the conductive terminal pad and the second conductive pad. The conductive bridge includes an elevated span extending above and across the first conductive pad.

A semiconductor module includes at least two semiconductor elements connected in parallel; a control circuit board placed between the at least two semiconductor elements; a control terminal for external connection; a first wiring member that connects the control terminal and the control circuit board; and a second wiring member that connects a control electrode of one of the at least two semiconductor elements and the control circuit board, wherein the second wiring member is wire-bonded from the control electrode towards the control circuit board, and has a first end on the control electrode and a second end on the control circuit board, the first end having a cut end face facing upward normal to a surface of the control electrode and the second end having a cut end face facing sideways parallel to a surface of the control circuit board.

A semiconductor package comprises a lead frame, a chip, and a molding encapsulation. The lead frame comprises one or more die paddles, a first plurality of leads, and a second plurality of leads. A respective end surface of each lead of the first plurality of leads and the second plurality of leads is plated with a metal. A first respective window on a first side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A second respective window on a second side of each lead of the first plurality of leads and the second plurality of leads is not plated with the metal. A method for fabricating a semiconductor package comprises the steps of providing a lead frame array, mounting a chip, forming a molding encapsulation, and applying a cutting process or a punching process.

A semiconductor package includes a package substrate including an insulating layer having an upper surface and a lower surface and provided with a first region which is recessed to a first depth from the upper surface toward the lower surface, a redistribution wiring buried in the insulating layer, a chip connection pad on a bottom surface of the recessed first region and connected to the redistribution wiring, and a wire connection pad on the upper surface of the insulating layer and connected to the redistribution wiring, a first semiconductor chip overlapping, in a top-down view of the semiconductor package, the recessed first region of the insulating layer and comprising a first chip pad connected to the chip connection pad of the package substrate, and a second semiconductor chip on the first semiconductor chip and connected to the wire connection pad of the package substrate through a conductive wire.

A method of determining a bonding status between a wire and at least one bonding location of a workpiece is provided. The method includes the steps of: (a) bonding a portion of a wire to a bonding location of a workpiece using a bonding tool of a wire bonding machine; (b) determining a motion profile of the bonding tool for determining if the portion of the wire is bonded to the bonding location, the motion profile being configured to result in the wire being broken during the motion profile if the portion of the wire is not bonded to the bonding location; and (c) moving the bonding tool along the motion profile to determine if the portion of the wire is bonded to the bonding location. Other methods of determining a bonding status between a wire and at least one bonding location of a workpiece are also provided.

Provided is a semiconductor module including a main circuit portion, a plurality of circuit electrodes, a plurality of main terminals, and a plurality of wires, in each of semiconductor chips, transistor portions and diode portions have a longitudinal side in a second direction, each of semiconductor chips has a plurality of end sides including a gate-side end side, each of the gate-side end sides is arranged facing a same side in a top view, the plurality of main terminals are arranged on a same side in relation to the main circuit portion so as not to sandwich the main circuit portion in a top view, each of the plurality of wires has a bonding portion, and a longitudinal direction of the bonding portion has an angle in relation to the second direction.

In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.