RC-network components that include a substrate having a capacitor with a thin-film top electrode portion at a surface at one side of the substrate. The low ohmic semiconductor substrate is doped to contribute 5% or less to the resistance of the RC-network component. The resistance in series with the capacitor is controlled by providing a contact plate, spaced from the top electrode portion by an insulating layer, and a set of one or more bridging contacts in openings in the insulating layer. The bridging contacts electrically interconnect the top electrode portion and contact plate. Different resistance values can be set by appropriate selection of the number of bridging contacts. Temperature concentration at the periphery of the openings is reduced by providing reduced thickness portions in the insulating layer around the periphery of the openings.

The present disclosure provides a method of forming a capacitor array and a semiconductor structure. The method of forming a capacitor array includes: providing a substrate, the substrate including an array region and a non-array region, wherein a base layer and a dielectric layer are formed in the substrate, and a first barrier layer is formed between the base layer and the dielectric layer; forming, on a surface of the dielectric layer, a first array definition layer and a second array definition layer respectively corresponding to the array region and the non-array region; forming a pattern transfer layer on a surface of each of the first array definition layer and the second array definition layer; patterning the dielectric layer and the second array definition layer by using the pattern transfer layer as a mask, and forming a capacitor array located in the array region.

A semiconductor device includes: a lower electrode; a first dielectric layer provided on the lower electrode; a first upper electrode provided on the first dielectric layer; a second dielectric layer provided on the first upper electrode; a second upper electrode provided on the second dielectric layer and electrically connected to the lower electrode; a third dielectric layer provided on the second upper electrode; and a third upper electrode provided on the third dielectric layer and electrically connected to the first upper electrode, wherein a first capacitor between the lower electrode and the first upper electrode, a second capacitor between the first upper electrode and the second upper electrode, and a third capacitor between the second upper electrode and the third upper electrode are connected in parallel with each other.

A semiconductor device includes: a lower electrode; a first dielectric layer provided on the lower electrode; a first upper electrode provided on the first dielectric layer; a second dielectric layer provided on the first upper electrode; a second upper electrode provided on the second dielectric layer and electrically connected to the lower electrode; a third dielectric layer provided on the second upper electrode; and a third upper electrode provided on the third dielectric layer and electrically connected to the first upper electrode, wherein a first capacitor between the lower electrode and the first upper electrode, a second capacitor between the first upper electrode and the second upper electrode, and a third capacitor between the second upper electrode and the third upper electrode are connected in parallel with each other.

An integrated circuit (IC) substrate manufacturing process provides time-dependent device characteristic variation due to hydrogen absorption by including one or more gettering layers near the devices that would otherwise absorb hydrogen and exhibit the variation as the hydrogen migrates in the devices. The method includes forming or mounting the devices on a top surface of the semiconductor wafer in die areas of the substrate, forming semiconductor structures in the semiconductor die areas, forming a getter layer above or adjacent to the devices in the die areas, and processing the wafer with one or more processes exposing the wafer to vapor having a hydrogen content, whereby an amount of hydrogen absorbed by the devices is reduced by presence of the getter layer. The method produces wafers including semiconductor dies with reduced hydrogen absorption by the devices and packaged ICs including the dies.

A semiconductor structure includes an interposer substrate having an upper surface, a lower surface opposite to the upper surface, and a device region. A first redistribution layer is formed on the upper surface of the interposer substrate. A guard ring is formed in the interposer substrate and surrounds the device region. At least a through-silicon via (TSV) is formed in the interposer substrate. An end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other, and are electrically connected to the first redistribution layer.

A semiconductor structure includes an interposer substrate having an upper surface, a lower surface opposite to the upper surface, and a device region. A first redistribution layer is formed on the upper surface of the interposer substrate. A guard ring is formed in the interposer substrate and surrounds the device region. At least a through-silicon via (TSV) is formed in the interposer substrate. An end of the guard ring and an end of the TSV that are near the upper surface of the interposer substrate are flush with each other, and are electrically connected to the first redistribution layer.

A package that includes a substrate, an integrated device coupled to the substrate, and an integrated passive device comprising at least two capacitors. The integrated passive device is coupled to the substrate. The integrated passive device includes a passive device substrate comprising a first trench and a second trench, an oxide layer located over the first trench and the second trench, a first electrically conductive layer located over the oxide layer the first trench, a dielectric layer located over the first electrically conductive layer, and a second electrically conductive layer located over the dielectric layer.

A semiconductor structure includes a first metal-dielectric-metal layer, a first dielectric layer, a first conductive layer, a second conductive layer, and a second dielectric layer. The first metal-dielectric-metal layer includes a plurality of first fingers, a plurality of second fingers, and a first dielectric material. The first fingers are electrically connected to a first voltage. The second fingers are electrically connected to a second voltage different from the first voltage, and the first fingers and the second fingers are arranged in parallel and staggeredly. The first dielectric material is between the first fingers and the second fingers. The first dielectric layer is over the first metal-dielectric-metal layer. The first conductive layer is over the first dielectric layer. The second conductive layer is over the first conductive layer. The second dielectric layer is between the first conductive layer and the second conductive layer.

An integrated circuit (IC) includes a semiconductor substrate and an interconnect region. The semiconductor substrate has a first surface and a second surface opposite the first surface. The semiconductor substrate has a first region with a passive component. The semiconductor substrate has a second region outside the first region. The resistance of the second region is smaller than the resistance of the first region. The interconnection region is on the second surface of the semiconductor substrate.